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 							B.TECH
SUBJECT: Digital Electronics    (Sep 2015)                                  BRANCH:  CSE 3rd SEM
SUBJECT CODE: EE-204-F                                            SEMESTER: III
Max Marks: 30                                                     DURATION:90 min.

Note: Question 1 is compulsory and Attempt 1 question from each section.

SOLUTION

Section - A

Q-1: Write short note on the following:

1(a) Reflected Gray Code Click to view the Solution

Answer: Gray code is also called as reflected gray code as the (N+1) bit code can be formed by reflecting an N bit code and appending ‘0’ with old code and ‘1’ with newly formed code. The code thus formed differs in one bit value only from one number to next or previous number. An example of forming gray code is shown below:The conversion of (52)10 to binary, octal and hexadecimal is shown below:


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1.(b) BCD Addition process, and perform the 68 - 24 using 9’s complement. Click to view the Solution
For +ve numbers write the 4-bit values for digits For –ve numbers, take 9’s complement, and write the 4-bit values for digits Add the numbers If addition of each nibble > 9 or Carry generated, Add 6 to result +68 = 068 -24 = 9’s complement of 024 = 999 – 024 = 975
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1.(c ) c. What do you understand by Don’t Care condition, how are they helpful in solving the equation using K-Map Click to view the Solution

Don’t care conditions are those terms whose presence or absence does not matter much, however if they are used properly, they may help in simplifying the equation to great extent. They may be taken as ‘1’ for SOP and ‘0’ for POS if they help in forming the octet, quad or pair. hide this content


1.(d) Signed number representation, and write the advantages of 2’s complement representation over 1’s complement system Click to view the Solution

 Signed representation is used to represent both the +ve and the –ve numbers. There are following three type of signed number representation in binary system. These are:
a.	Signed magnitude Number: In this representation one additional bit is needed at MSB position to indicate whether the number is +ve or –ve. Thus if there are N bits then N-1 bits are used for magnitude and Nth bit indicate sign.The range of representable numbers are +/- 0 to +/- 2N – 1.
b.	1st complement representation: In this the magnitude is complemented to get the –ve number. The sign bit is also made equal to ‘1’ to indicate –ve number. For example to represent – 35 using 1’s complement we will do as:
+35			       =   0100011
-35 in 1’s complement   =   1011100 ; obtained by making ‘0’ as ‘1’ and vice versa
c.	2’s Complement representation: The –ve number is representing by 1st taking the 1’s complement of the magnitude and appending 1 at MSB and adding 1 to it. As an example -35 in 2’s complement is written as:
+35 			=	0100011
-35 in 1’s complement	=	1011100
Adding ‘1’			     +1
We get -35 in 2’s complement= 1011101
Advantage of 2’s complement system: 
i.	There is only one zero as against two zero in other representation
j.	Addition and subtraction is performed only by addition process
k.	End around carry is ignored


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Section - B

Q.2. Why is it necessary to use Hamming code? A receiver received the following Hamming code 0011100101101 with odd parity. Find the error in the received code and write the correct code that was transmitted by the receiver. Click to view the Solution

13 12 11 10 9 P8 7 6 5 P4 3 P2 P1
0 0 1 1 1 0 0 1 0 1 1 0 1
We find P1= check ‘1’ leave ‘1’: check 1,3,5,7,9,11,13	= Even (Four ‘1’s) Parity
	P2= Check 2, leave 2 I.e check 2,3,6,7,10,11	= Even  	(Four ‘1’s) Parity
	P4= Check 4, leave 4 I.e check 4,5,6,7,12,13	= Even (Two ‘1’s) Even parity
	P8= Check 8, leave 8 I.e check 8,9,10,11,12,13	= Odd
Parity  P8   P4   P2   P1
	0    1      1     1	= 7; therefore 7th bit is in error
So the correct code transmitted is: 0011101101101

       
       
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2.(b) Simplify F(ABCD) = ∑m (0,1,5,9,13,14,15) +d(3,4,7,10,11 using K-Map. Click to view the Solution

1st of all name the boxes as per the minterms. These are shown in bottom right corner of each box. Enter the ‘1’ against the minterms and ‘X’ against the don’t care terms.

If we consider don’t care terms 3,7,11 as ‘1’s then we can form an octet with terms (1,3,5,7,13,15,9,11) Similarly, Quad at the top is formed with terms (0,1,4,5) and Quad at bottom (10,11,14,15) The solution obtained is :

F(ABCD) = A’C’ + AC + D

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Q.3. (a) Explain the Mc-Clusky method of solutions of Boolean equation. Solve the following equation using the Mc-Clusky method. F(ABCD) = ∑m (20,28,37,39,48,56)
Click to view the Solution

Mintermsm20m28m37m39m48m56
Binary010100011100100101100111110000111000
No. of 1's233423

Now Grouping these terms as per no. of 1's 3
2m20010100m20-m2801-100A'BDE'F'
m48110000m48-m5611-000ABD'E'F'
m28011100m37-m391001-1AB'C'DF
m37100101
m56111000
4m39100111

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Q. 3.(b)Minimize the following standard POS expression using K-Map and implement the circuit using NOR gates. F = ΠM (0,2,3,5,7) Click to view the Solution

The K-Map will have 0’s as entry in the boxes of the MAXTERMS given in question. It has one quad, and two pairs.

There are three pairs formed
Top corner pair formed with Maxterms 0,2 gives ( A + C)
The 2nd pair formed with Maxterms 2,3 gives  :  A + B'
The 3rd pair formed with Maxterms m5,m7 gives ()A' + C')
Thus the solution is F(ABC) = (A' + C') . (A + B') . (A + C)

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Section - C

Q.4. (a) Design a Half Adder. Click to view the Solution

A half adder is a combinational circuit that adds two bits as shown in the following truth table.

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

From the truth table, the SOP equations for the half adders are obtained and given below:

Sum = A'B + AB
= A ⊕ B
Carry = AB
The logic circuit diagram of HA is given below:



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Q.4. (b) Show that a full Adder can be constructed with two half Adders and an OR-gate. Click to view the Solution

Ans: A full adder is a circuit that adds 3-bits, two that of the two numbers and the third as the carry of the previous stage. The sum of these three bits are shown in the table below:

A

B

C

Sum

Carry

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1


The SOP equation for the Sum = A’B’C + A’BC’ + AB’C’ + ABC
The SOP equation for the Carry =A’BC + AB’C + ABC’ + ABC
The algebraic solution of the equations are given below:
Sum = A’B’C + A’BC’ + AB’C’ + ABC
=A’(B’C + BC’) + A(B’C’ + BC)
= A’(B ⊕ C) + A(B ⊕ C)'
= A ⊕ ( B ⊕ C )
The algebraic solution of the equations are given below:
Carry =A’BC + AB’C + ABC’ + ABC
= BC(A’ + A) + A(B'C + BC')
= BC + A ( B ⊕ C )
The logic Circuit for the above solution is:



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Q.5(a) Design a comparator circuit that compares two 2-bit numbers. Click to view the Solution

Ans:
A comparator circuit is one that compares two numbers and produces the result as EQUAL, GREATER or LESS. Here in the problem we are to design a comparator circuit that will compare two 2-bit numbers and produce the three output.
Functional table for two bit comparison

Input A

Input B

Outputs

A1

A0

B1

B0

A>B

A<B

A=B

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

1

0

0

1

0

0

0

1

0

1

0

0

1

0

1

1

0

0

1

0

0

1

1

1

0

1

0

1

0

0

0

1

0

0

1

0

0

1

1

0

0

1

0

1

0

0

0

1

1

0

1

1

0

1

0

1

1

0

0

1

0

0

1

1

0

1

1

0

0

1

1

1

0

1

0

0

1

1

1

1

0

0

1


The Logic output equations written using the minterms from the truth table re given below:
G=A>B = A1'A0B1'B0' + A1A0'B1'B0' + A1A0'B1'B0 + A1A0B1'B0' +A1A0B1'B0 + A1A0B1B0'
L=A < B = A1'A0'B1'B0 + A1'A0'B1B0' + A1'A0'B1B0 +A1'A0B1B0' + A1'A0B1B0 + A1A0'B1B0
EQ=A=B=A1'A0'B1'B0' + A1'A0B1'B0 + A1A0'B1B0' + A1A0B1B0
The Simplifications for the above Boolean equations:

Figure: K-Map of the comparator Boolean Equations for AB, A==B
(a). A>B
G=A1B1' + A0B1'B0' + A1A0B0'
(b) A L=A (c ) A==B
EQ=A==B = A1'A0'B1'B0' + A1'A0B1'B0 + A1A0'B1B0' + A1A0B1B0
= A’1A’0B’1B’0 + A’1A0B’1B0 + A1A’0B1B’0 + A1A0B1B0
= A'0B'0( A'1B'1 + A1B1) + A0B0( A'1B'1+A1B1)
= ( A'1B'1 + A1B1)( A'0B'0 + A0B0)
= (A1 ⊕ B1)' ( A0 ⊕ B0)'
The simplified three equations for the comparator circuit are:
G = A1B’1 + A0B’1B’0 + A1A0B’0
L = A’1B1 + A’1A’0B0 + A’0B1B0
EQ = (A1 ⊕ B1)' ( A0 ⊕ B0)'
Based on the above simplified boolean equations, the logic circuit is implemented as given below:


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(b) Write short note on Multiplexer Click to view the Solution

Ans:
A multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2ninputs has n select lines, which are used to select which input line to send to the output. In general, a MUX (multiplexer) has 2^N inputs, N control lines and a single output. This is shown in the following figure.



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