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 							B.TECH
SUBJECT: Digital Electronics                                      BRANCH:  CSE /ECE/EE
SUBJECT CODE: EE-204-F                                            SEMESTER: III
Max Marks: 30                                                     DURATION:90 min.

Note: Question 1 is compulsory and Attempt 1 question from each section.

SOLUTION

Q.1.(a) Convert (52)10 into binary, octal and hexadecimal system Click to view the Solution

The conversion of (52)10 to binary, octal and hexadecimal is shown below:


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1.(b) Represent (+29) 10 and (-76) 10 in sign & magnitude, 1’s Complement, 2’s complement representation Click to view the Solution
Representation of +ve number in all the system of representation is same. Therefore:
(+29) 10 in sign & magnitude = 0 0011101
(+29) 10 In 1’s Complement = 0 0011101
(+29) 10 In 2’s complement representation = 0 0011101
Representation of –ve number in different representation is done as follows:
i. (-76) 10 in sign & magnitude: In this representation sign bit for –ve number is taken as ‘1’, and the magnitude is taken same as for +ve number.
Thus (-76) 10 = 1 01001100
ii. (-76) 10 in 1’s Complement require complementing each bit of the magnitude of the 76 and affixing ‘1’ as sign bit at MSB.
Thus (-76) 10 = 1 10110011
iii. (-76) 10 in 2’s complement representation. Is done by performing 1’s complement of the magnitude of 76 and a1 to it and finally affixing ‘1’ sign bit at MSB position.
Thus (-76) 10 = 1 10110100
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1.(c ) Find the 1’s and 2’s complement of (+54)10 and (+38)10 Click to view the Solution

1’s complement of a number is done by complementing each bit of the number including the sign bit. 2’s complement of any number is performed by writing the 1’s complement of the number and adding 1 to it. Thus

Number

1’s Complement

2’s Complement

 (+54) 10
= 0 00110110

(+54) 10               = 0 00110110
1’s complement= 1  11001001
So (-54)   =    1  11001001

(+54) 10                               = 0 00110110
1’s complement                  = 1  11001001
2’s Complement                 +                    1
-  - - - - - - - - -
So (-54)                               = 1 11001010   

 (+38) 10

(+38) 10               = 0 00100110
1’s complement= 1  11011001
So (-38)    =  1  11011001

(+38) 10                               = 0 00100110
1’s complement                  = 1 11011001
2’s Complement                 +                    1
---- - - -- - - -  - - - -
So (-38)                                = 1 11011010   


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1.(d) Add (+86) and (-25) using 1’s and 2’s complement system. Click to view the Solution

Addition in 1’s Complement :
			+86	=	0 01010110
			+25	=	0 00011001
(-25) = 1’s complement  of +25	=	1 11100110
Adding +86 and  -25 (i.e. 1’s complement of (+25)
					0 01010110
				+	1 11100110
- - - - - - - - - - - - -- - - - - -- - - ------------------------------- - - -- - - - - - - -
		   		=      1  000111100	, we find that as a result of addition a carry is generated
In 1's complement, we add this carry with LSB	+1
- - - - - - - - - - - - -- - - - - -- - - - - - -- - - - - - - --------------------------------
					0 00111101
- - - - - - - - - - - - -- - - - - -- - - - - - -- - - - - - - ----------------------------------
As seen MSB=0, indicating result is +ve, and its magnitude is = (+61)10
Addition of (+86) and (-25) using 2’s Complement Representation:
				+86	=	0 01010110	
				+25	=	0 00011001
(-25) = 1’s complement  of +25		=1 11100110
Adding 1 to get 2’s complement of 25, 	+  1
So, -25 in 2’s complement 		= 1 11100111
Adding +86 and  -25 (i.e. 2’s complement of (+25)
					0 01010110
				+	1 11100111
- - - - - - - - - - - - -- - - - - -- - - - - - -- - - - - - - -
				 = 1 000111101
In 2’s complement addition, the carry if any is to be ignored.
Therefore (+86) and (-25) = 000111101 which is = (+61)10


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1.(e) Write the gray codes of decimal number 0 to 7. Click to view the Solution

Gray code also called a reflected code. In this, there is only one-bit change as go to higher or the lower number. The gray code for the decimal 0 to 7 is shown below:

Decimal

Gray Code

0

000

1

001

2

011

3

010

4

110

5

111

6

101

7

100


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Sec- A
Q.2. (a) Simplify the following Boolean equation: F(ABCD) = ∑m (0, 2,3,6,7, 8,10) + ∑d(4,12,13,15) Click to view the Solution

The K-Map of 4 variable for the function F(ABCD) and its solution is given below:
In the K-Map, we get two quads, one using the 1's in the four corners, and another four 1's with the minterms (2,3,6,7). Each quad eliminates two variables.

The don’t care conditions are treated as zeros in the above K-Map as there is no 1’s left for further combinations. Thus, the solution for the function F(ABCD) is:

F(ABCD)   =  A’C + B’D’ 

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2.(b) Give the simplified Design equations using K-Map for a three variable digital circuit that gives a high output when maximum number of input variable have high value. The input combination “000” is taken as the don’t care condition and the rest combination of inputs gives a low output. Click to view the Solution

Analyses of the above statement points that has three inputs and the combinations that have maximumum number f 1’s are 011, 0101, 110 and 111 which have high outputs. These are shown in th TT below:

Binary inputs

Output

Minterms

ABC

Y

 

000

X

 

001

0

 

010

0

 

011

1

A’BC

100

0

AB’C’

101

1

AB’C

110

1

ABC’

111

1

ABC


The SOP equation will be F(ABC) = ∑m (3,5,6,7) whose solution by K-Map is given below:


The don’t care condition doesn’t help in any way for further simplification and hence may be treated as zero. The final SOP simplification for the function is given below:,

F(ABC) = AB + BC + AC

The logic circuit for the implementation is given below:



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Q.3. (a) Simplify the following equation: F(ABC) = ∏M( 1,3,6,7) Click to view the Solution

the given equation it is clear that the the equation is in POS form. So in K-Map we group zero’s and the vlues are read by complementing 0’s with 1’s, 1’s with 0’s and . with +.
The POS solution is therefore given below:

		F(ABC) = (A+C’)(A’+B’)

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Q. 3.(b) Simplify the SOP equation : F(WXYZ) = W’X’YZ, W’X’YZ’ + W’XYZ’ + WX’YZ + WXY’Z’ + W’XYZ + WX’Y’Z’ + WX’Y’Z Click to view the Solution

The K-Map will have 1’s as entry in the boxes of the minterms given in question. It has one quad, and two pairs.

The quad gives the solution as :  W’Y
The pairs  gives the solution as :  WY’Z’
The 2nd pair gives the solution as :  WX’Z
Thus the total solution is :
F(WXYZ) = W’Y + WY’Z’ + WX’Z

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Q.4. (a) Design a full adder circuit. Click to view the Solution

Ans: A full adder is a circuit that adds 3-bits, two that of the two numbers and the third as the carry of the previous stage. The sum of these three bits are shown in the table below:

A

B

C

Sum

Carry

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1


The SOP equation for the Sum = A’B’C + A’BC’ + AB’C’ + ABC
The SOP equation for the Carry =A’BC + AB’C + ABC’ + ABC
The algebraic solution of the equations are given below:
Sum = A’B’C + A’BC’ + AB’C’ + ABC
=A’(B’C + BC’) + A(B’C’ + BC)
= A’(B C) + A(B + C)'
= A B C
The algebraic solution of the equations are given below:
Carry =A’BC + AB’C + ABC’ + ABC
=C(A’B + AB’) + AB(C + C ')
= C( A B ) + AB
The logic Circuit for the above solution is:


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4.(b) Design a parallel 4-bit subtractor circuit. Click to view the Solution

Ans: The example below shows how to subtract two multi-bit numbers. Let number A=101100 and number B be 100001. The subtraction is done as follows:

Thus we observe that vertically at each stage of subtraction, we have three bits to be subtracted, hence for the above given problem, we would need as many full subtractors as there are number of bits in each number. Therefore for the given problem, we would require four full subtractors connected in cascade as shown below:
Figure-: A 4-bit Binary Subtractor circuit Block Diagram Each block (FS) in the above figure are the full subtractor. Thus they can be replaced with the logic diagram of the full subtractor, such that the borrow from the least significant block is connected to the next stage. Hence the complete circuit is nothing but an extension of the Full-Subtractor and is given below:
The subtraction of two 4-bit number can be explained by working from right to left in figure-3 and figure-4. The operation of the above subtractor is given below with Ai and Bi as input numbers Ci as borrow in. Internal borrows are Br0, Br1-------Br3: 1. With A0 =1, and B0 =0, Cin =1 initially, the output of the subtractor circuit will be a D0=1, and Br1 =0
2. With A1 =0, and B1 =1, and Br1 =0 which is connected to C1, the output of subtractor will be a D1=1, and Br1 =1
3. With A2 =1, and B2 =0, and Borrow Br1 =1 from stage-1, the output of subtractor will be a sum D2=0, and Br2 =0
4. With A3 =1, and B3 =1, and the borrow Br2 =0 from stage-1, the output of subtractor will be a D3=0, and Br3 =0
The final output of the circuit on performing subtraction on two four-digit numbers A=11012 (addend) and B=10102 (augend) i.e. 13-10 is D3 D2 D1 D0= 0011 with Borrow= 0

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Q.5. (a) Design a comparator circuit that compares two 2-bit numbers. Click to view the Solution

Ans: A comparator circuit is one that compares two numbers and produces the result as EQUAL, GREATER or LESS. Here in the problem we are to design a comparator circuit that will compare two 2-bit numbers and produce the three output. This is illustrated in the block diagram given below:

Functional table for two bit comparison

Input A

Input B

Outputs

A1

A0

B1

B0

A>B

A<B

A=B

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

1

0

0

0

1

1

0

1

0

0

1

0

0

1

0

0

0

1

0

1

0

0

1

0

1

1

0

0

1

0

0

1

1

1

0

1

0

1

0

0

0

1

0

0

1

0

0

1

1

0

0

1

0

1

0

0

0

1

1

0

1

1

0

1

0

1

1

0

0

1

0

0

1

1

0

1

1

0

0

1

1

1

0

1

0

0

1

1

1

1

0

0

1


The Logic output equations written using the minterms from the truth table re given below:
G=A>B = A1'A0B1'B0' + A1A0'B1'B0' + A1A0'B1'B0 + A1A0B1'B0' +A1A0B1'B0 + A1A0B1B0'
L=A EQ=A=B=A1'A0'B1'B0' + A1'A0B1'B0 + A1A0'B1B0' + A1A0B1B0
The Simplifications for the above Boolean equations:

Figure: K-Map of the comparator Boolean Equations for AB, A==B
(a). A>B
G=A1B1' + A0B1'B0' + A1A0B0'
(b) A L=A (c ) A==B
EQ=A==B = A1'A0'B1'B0' + A1'A0B1'B0 + A1A0'B1B0' + A1A0B1B0
= A’1A’0B’1B’0 + A’1A0B’1B0 + A1A’0B1B’0 + A1A0B1B0
= A'0B'0( A'1B'1 + A1B1) + A0B0( A'1B'1+A1B1)
= ( A'1B'1 + A1B1)( A'0B'0 + A0B0)
= (A1 ⊕ B1)' ( A0 ⊕ B0)'
The simplified three equations for the comparator circuit are:
G = A1B’1 + A0B’1B’0 + A1A0B’0
L = A’1B1 + A’1A’0B0 + A’0B1B0
EQ = (A1 ⊕ B1)' ( A0 ⊕ B0)'
Based on the above simplified boolean equations, the logic circuit is implemented as given below:


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(b) Design a full subtractor circuit. Click to view the Solution

Ans: Ans: A full Subtractor is a circuit that subtracts 3-bits, two that of the two numbers and the third as the borrow from next stage. The subtraction of these three bits are shown in the table below:

A

B

C

Dif

Borrow

0

0

0

0

0

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

1

1

1

1

1


The SOP equation for the Diff = A’B’C + A’BC’ + AB’C’ + ABC
The SOP equation for the Borrow =A’B’C + A’BC’ + A’BC + ABC
The algebraic solution of Diff. the equations are given below:
Diff = A’B’C + A’BC’ + AB’C’ + ABC
=A’(B’C + BC’) + A(B’C’ + BC)
= A’(B C) + A(B C)’
= A B C
The algebraic solution of the Borrow equations are given below:
Borrow = A’B’C + A’BC’ + A’BC + ABC
=A’(B’C + BC’) + BC(A’ + A)
= A’( B C ) + BC
The logic Circuit for the above solution is:



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