` 							B.TECH Sep 2014`
`SUBJECT: Microprocessor and Interfacing                           BRANCH:  CSE /ECE/EE`
`SUBJECT CODE: EE-309-F                                            SEMESTER: V`
`Max Marks: 30                                                     DURATION:90 min.`

`Note: Question 1 is  compulsory and Attempt 1 question from each section.`

`					SOLUTION`
Q.1. (a) Calculate the number of memory chips needed to design 8K-byte memory if the memory chip size is 1024x4.Click to view the Solution

Ans: No. of Chips = (Size of memory Desired / Size of each memory chip)
= 8 K-Byte / 1024 x4
= 8 x 1024 x 8 / 1028 x4
= 16
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(b) Describe MVI, LDA, HLT instructions of 8085Click to view the Solution
Ans: (i) MVI: It is a data transfer instruction of 8085, and is used to transfer an immediate byte to a register or a memory location. The format of the instruction is MVI R/M, 8-bit data. Examples of this instruction are:
MVI A, 25h;
MVI M, 55h
(ii). LDA: Load accumulator with content from the memory whose address is specified in the instruction. Instruction format: LDA 16-bit address
Example: LDA 2050h; this instruction will copy a byte from memory location 2050h into the accumulator.
(iii). HLT: This is a processor control instruction. The processor stops execution of the program when HLT instruction is encountered. This instruction does not require any operand. Hide this content

( c) Name the 8086 Flags. Click to view the Solution

The different flags of 8086 processor are shown in figure below:

(i) CF :- Carry Flag (ii) PF:- Parity Flag
(iii) AF :- Auxilary Flag (iv) ZF :- Zero Flag
(v) SF :- Sign Flag (vi) TF :- Trap Flag
(vii) IF :- Interrupt Flag (viii) DF :- Direction Flag
(ix) OF :- Oveflow Flag

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(d) Explain the flags affected by adding (+7B) and (+36) Click to view the Solution

Ans:
7B = 01111010
36 = 00110110
+
- - - - - - - - - - - - - - - - - - - - - -
= 10110000 - - - - - - - - - - - - - - - - - - - - - -
The status of the processor is indicated in the flag register as indicated below:

 Flags of 8085 Microprocessor 7 6 5 4 3 2 1 0 SF ZF - AF - PF - CF 1 0 1 0 0 0

So we see that the sign flag, auxiliary flag get affected with the addition of 7B and 36
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(e) Explain the shift and rotate instructions Click to view the Solution

Ans: 8085 Processor supports the following instructions for shift and rotate operation:
RLC: Rotate Accumulator Left :
RAL: Rotate accumulator left through carry
RRC: Rotate Accumulator Right
RAR: Rotate Accumulator Right through Carry

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### Sec- A

Q.2. (a) Describe the internal architecture of the 8085 microprocessor. Click to view the Solution

The figure below shows the internal architecture of 8085 Microprocessor

Figure : The internal architecture of the 8085 microprocessor.
The different units are part of the internal architecture of 8085 are described below:
ALU
Arithmetic and Logic unit processes the data supplied to it either from memory, registers or i/o. It is an 8-bit ALU which accepts two 8-bit data, processes them and produces an 8-bit output. All the operations of 8085 assumes accumulator as one of the register to hold the data and/or result.
Register Array:
8085 uses a number of general purpose, special purpose and flag register for all the operations. The general purpose register B, C, D,E,H,L are 8-bit in size but could be used in pair BC, DE, HL for 16-bit operations. Special purpose registers are Stack Pointer (SP), Program Counter (PC), and two register W and Z are used to hold 8-bit data during the execution of some of the instructions. Registers W and Z are not visible to the programmer. Flag register (also called as Program Status word ‘PSW’) is used to hold the status information of the current operations of the processor.
The address data buffer can both send and receive data from internal data bus. It receives data from external bus and loads it on the internal bus and vice versa. For addressing purpose the address contained in the stack pointer or the program counter are loaded onto the address bus from address buffers.
8085 has 16-bit address bus and 8-bit data bus. Internally the lower 8-bit of address bus are time multiplexed with the data bus, and thus carries the AD7 –to- AD0 and is made separate by using an address latch. 8085 has an address latch enable signal (ALE), that enables the address latch for a short time to latch the address at the output of the latch. After the address is latched the bus can be used to the send/receive the data.
Instruction Register and Decoder
8085 has a special purpose 8-bit Instruction register, this register is not visible to the programmer. Instruction fetched from memory is directed to instruction register and then sent to the instruction decoder. The Instruction decoder is used to decode the instruction in IR and establishes a sequence of events to follow.
Timing and Control Unit
Timing and control unit is a very important unit as it synchronizes the operations of the 8085 with the clock including the ALU, and flow of data through various registers and other units. This unit consists of an oscillator and controller sequencer which sequences the micro-instructions which generate the necessary control signals needed for internal and external units.
The oscillator generates two-phase clock signals which aids in synchronizing all the registers of 8085 microprocessor. The signals are associated with Timing and control unit are: READY, RD’, WR’, ALE, S0, S1, IO/M’, HOLD, HLDA, RESET IN, RESET OUT
Serial I/O control Unit:
This unit is used for serial I/O activity. 8085 has two pins (SID and SOD) for this purpose .
Interrupt Controller:
This unit is used to service an interrupt request from an external device. Whenever 8085 receives an interrupt request on one of its interrupt line (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR ), the microprocessor shifts the control from main program to process the incoming request and after the completion of request, the control goes back to the main program. Of the five interrupt pins, TRAP is non-maskable and has the highest priority, the others three (RST 7.5, RST 6.5, RST 5.5) are maskable and have lower priority than TRAP. INTR has the lowest priority signal on 8085. INTA’ pin is used to acknowledge the interrupt requests.
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(b) Define Interrupt ? Explain the interrupt structure of 8085.click here to see solution:
Ans:
An interrupt is an event, a signal or a request that is initiated by a device attached to a computer/system or from a running program indicating to the system that an event needs an immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing. After an interrupt is received the microprocessor temporarily stops the execution of main program and transfers control to interrupt service routine. After carrying out its task, the control is transferred back to main program.
Interrupt structure of 8085.
8085 supports both the software and the hardware interrupts. The software interrupts are initiated by RST instructions included in the 8085 instruction set. There are 8 RST instructions RST 0 –to – RST 7. RST instructions are commonly used to setup the software break-points as a debugging technique. So the breakpoint is a Restart (RST) instruction in a program whare the execution of the program stops temporarily and the program control is transferred to the RST location. This allows the user to examine memory location or registers whenever a specific key is pressed. These instructions are executed similar to the CALL instructions. That is whenever RST instruction is executed the address of the next instruction is stored on the stack before the control is transferred to the software routine. The program will return from the interrupt handler on encountering return (RET) instruction.
The hardware interrupt can occur on TRAP, RST 7.5, RST 6.5, RST 5.5, INTR pins of the 8085. These interrupts are classified as Maskable or Non-maskable and Vectored or non-vectored interrupts. Of the above four interrupts TRAP is a Non-Maskable interrupt and other three (RST 7.5, RST 6.5, RST 5.5) are maskable interrupts.
A non-maskable interrupt is an interrupt which is given the highest priority in the order of interrupts. Suppose you want an instruction to be processed immediately, then you can give the instruction as a non-maskable interrupt. Further the non-maskable interrupt cannot be disabled by programmer at any point of time. The maskable interrupts can be disabled and enabled using EI and DI instructions. Among the maskable interrupts RST 7.5 is given the highest priority above RST 6.5 and least priority is given to INTR.
Figure below shows the 8085 interrupts and their vector locations.

Figure shows that whenever the interrupt ‘TRAP’ is triggered, the program control is transferred to location 0024h without any hardware or the interrupt enable EI instruction. TRAP is generally used for such critical events as power failure and emergency shut-off.
RST 7.5, RST 6.5, and RST 5.5 interrupts are enabled under program control with two instructions. These instruction are EI (enable interrupt) and SIM(set interrupt mask).
The entire interrupt process of 8085 (except TRAP) is disabled by resetting the Interrupt Enable (EI) flip-flop. This flip-flop can be reset in one of the following ways:
1. By DI instruction
2. By system Reset
3. On recognition of an interrupt request

All the vectored interrupts (TRAP, RST 7.5, RST 6.5, and RST 5.5) are automatically vectored to a specific location on memory page 00h without the need of any external hardware logic. The necessary logic is already implemented inside the 8085.

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Ans:
The microprocessor is a programmable device which process the data as per the instructions and produces the result for control or presentation to the outside world. The data which require to be processed may reside in registers, in memory or may even arrive from the i/o devices. So the addressing mode is a mechanism to access the data. 8085 microprocessor provides the following addressing modes to access the data.

6. These addressing modes are described in the following paragraph.
(i) Immediate Addressing Mode: This type of addressing mode is used to transfer an immediate byte (8-bit) data to one of the general purpose register or to a memory location. The immediate 8-bit data is part of the instruction as shown below:

The syntax and the examples of Immediate Addressing mode in 8085 are:
MVI Reg /M, 8-bit data
MVI B, 45h
MVI M, 37h
Before using the second instruction (MVI M, 8-bit data), the HL pair must be initialized to the memory.
(ii) Direct memory Addressing Mode: The direct memory addressing mode allows the data byte to be accessed from or written to the memory location whose address is specified in the instruction. When the system executes such instruction, it finds the address as part of the instruction. The microprocessor then loads this address on the address bus, and fetches the data from this address or stores the data at this address. This is shown in figure below.
8085 ports the following instruction as part of the Direct memory addressing mode :
a. LDA 16-bit address; as an example: LDA 2050h loads the accumulator with a byte from the memory location 2050h
b. STA 16-bit address; as an example: STA 2050h stores the data byte from the accumulator at the memory location 2050h
The register addressing mode allows the data byte to be copied from one register to another register. The source data of any data transfer instruction is not altered, but only the content of destination register is modified
.
The syntax is : MOV Reg, Reg
Examples are:
MOV B, C
MOV A, D
MOV E, H
In this addressing mode, the data is copied from the 16-bit address given in the register pair specified in the instruction, this type of instruction also allows to store the data from a source at an address given in the register pair specified in the instruction. The figure below shows the execution of such type of instruction.

The following instructions are the example of the Register Indirect Addressing Mode :
LDAX B/D; this instruction will copy the 8-bit data from the memory location whose address is given in the register pair (BC or DE) specified in the instruction.
STAX D; this instruction will store the 8-bit data from the accumulator to memory location whose address is given in the register pair (BC or DE) specified in the instruction.
The instructions of this type does not require any operand which provide data or the reference of the data. Instead the operand is assumed to be part of the instruction. The following figure shows the format of such instruction types.
The examples of this type of instruction are:
1. CLC
2. STC
3. CMA
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(b) Write a program in assembly language of 8085MP to add 10 numbers stored in memory location starting at location 2050h and store the result at location 2060 and carry at location 2061. Draw necessary flowchart of the process.click here to see solution:

### Sec-B

Q.4. (a) Describe the architecture of 8086 microprocessor with the help of the functional diagram.click here to see solution:
Figure below shows the architecture of 8086 microprocessor

The functional diagram above shows the different parts of the 8086 microprocessor. 8086 can be thought of divided in two functional units : (i) Bus Interface Unit (BIU)
(ii) Execution Unit (EU)
(i). Bus Interface Unit (BIU)
The bus interface unit is one through which the processor is connected to external world through the buses. It helps the EU by fetching the instructions and data from the memory. The bus interface unit generates the 20-bit physical address by manipulating the base address of one of the segment and the content of instruction pointer or the pointer and index register. For example CS : IP and DS:BX/SI/DI is used to generate the address of instruction from code segment and address of data from data segment respectively. It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions:
• Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.
The BIU has the following components:
a. Segment Register and Instruction Pointer: The segment registers are:
Code Segment Register
Data Segment Register
Stack Segment register
Extra Segment Register
And another register which is used to hold effective address of the instruction is called the instruction pointer.
b. Instruction Queue: 8086 microprocessor has a 6byte instruction, where the BIU prefetches the instructions while the EU is busy executing the instruction. This feature of the 8086 helps speed-up the operation of the 8086.
c. Bus Control Logic: The status codes (S0,S1,S2) of the CPU is used by the bus-controller to activate maximum mode memory control signals which are important for multiprocessor environment, supported by Maximum mode. In the maximum-mode, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessors sharing the system bus.
(ii). Execution Unit: The execution unit is the unit where the instructions of the user program are executed. The instructions from the queue which are fetched by the BIU are passed to execution unit. The EU decodes the instructions and the EU control unit generates the necessary control signals which help in coordinating the different activities of the processor during execution. The EU has the following parts:
a. General Purpose registers: This unit has four 16-bit general purpose registers as AX, BX, CX, DX, these registers can be used as 16-bit register or half register AL,AH,BL,BH, CL, CH, DL,DH for 8-bit operations.
b. Index and Pointer registers: These are 16-bit registers. The index registers are during string operations to hold the source and destination address in the memory for certain string related operations. The pointer registers are used to hold the offset address in the data or the stack segment. These registers may also be used to hold data temporarily.
c. ALU : This is the unit that actually performs the arithmetic and logical operations. It receives the data through the internal data bus manipulates the data as per the instruction and loads the result back on the data bus for transfer to the destination defined in the instruction.
d. Flag Register: The flag register also known as Program Status Word(PSW) is used to hold the status of the ALU operation. It indicates by its bit value that certain type of conditions which the programmer can use in his program for decision making and branching to other areas of the program for carrying out certain tasks. The different flags of 8086 microprocessor are: Carry Flag, Parity Flag, Auxiliary Carry Flag, Zero Flag, Sign Flag, Trap Flag, Interrupt Flag, Direction Flag and the Overflow Flag.
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(b) Explain the programming model of 8086 microprocessor.click here to see solution:

Ans:

The programming model of 8086 describes the registers that are visible to a programmer. The programmer uses these registers to contain the data or the result of an operation which are further requires to be processed by the ALU with the subsequent data or it may be sent to external world through memory. The following paragraph describes the registers which used by programmer.
• Data Group of Registers: These registers are also called the general purpose registers and are used to store both the operands and the result. These are all 16 bit registers and each of these registers can be used as a whole 16 bit register or as part (8 bit) register. The register AX is used as accumulator and the register BX, CX and DX in addition to being general purpose registers can also be used for special purpose for addressing, counting and i/o roles as given below:

 AX Accumulator BX base register CX Used as counter. DX to hold i/o address during certain i/o operations

• Pointer and Index Registers: These registers includes the base (BP), index (SI, DI) and also the program counter(IP) and the stack pointer(SP). These registers are used in forming the effective address of an instruction. To provide flexible base and index addressing, a data address may be formed by adding together the combination of BX or BP register contents, index (SI or DI) register content and the displacement. The resulting address is called effective address (EA).i.e. EA=base Register Contents+ Index register Contenets + 8/16 bit displacement.
• Segment Registers: The 8086 memory is divided into four overlapping segments. The starting address of each segment is stored in the corresponding segment registers. These are:

 Segment Register Full Name CS Code Segment Register DS Data Segment Register SS Stack Segment Register ES Extra Segment Register

The physical address of a data or an instruction is formed by adding the content of the segment register and the effective address formed by adding base, index and the displacement. PHY ADD = EA + Beginning of Segment Address.
• FLAG (STATUS) REGISTER or Program Status Word (PSW):
The 8086 has a 16 bit flag register of which only 9 bits are used as flags and the rest 7 bits are not used. These flags are set or reset after the operation in an ALU. Six of the flags are status indicators, reflecting properties of the result of the last arithmetic or logical instructions. These are CF, AF, PF, ZF, SF and OF. The 8086/88 has several instructions that can be used to transfer program control to a new memory location based on the state of the flags. Three of the flags can be set or reset directly by the programmer and are used to control the operation of the processor. These are TF, IF, and DF. All the flags are discussed in the following paragraph

Q.5. (a) Explain with suitable examples the various flags of 8086 microprocessor.click here to see solution:

Ans: PSW or the flag register is a 16-bit register o which 8-bits are used in 8086 and this is shown below:

These flags are explained in the following paragraph.

 No. Name of Flag Purpose 1 Carry Flag (CF): Carry flag (CF) is set if there is a carry-out or a borrow-in for the most significant bit of the result during the execution of an instruction. Otherwise, CF is reset. An example of 2’s complement: A= 0000000001100101 B= 1111111111000011 - -  - - -- - - - - - -    1,0000000000101000 - - - - - - - - - - - - As seen from this example, a carry is generated, and hence, the carry flag get set to ‘1’. 2 Parity Flag (PF): PF is set if the result produced by the instruction has even parity-that is, if it contains an even number of bits at the 1 logic level. If parity is odd, PF is reset. A= 000000000101010 B= 000000000010010 -- - - - - - - - - - + =000000000111100 - - - - - - - - - - - As a result of adding A and B we get four 1’s in the result. That is, the result has even number of 1’s, so the parity of the result is even and hence, the parity flag is set to 1. If there were odd number of 1’s in the result, parity flag would have reset. 3 Auxiliary carry Flag (AF): Auxiliary Carry (AP) is set if there is a carry-out from the low nibble into the high nibble or a borrow-in from the high nibble into the low nibble of the lower byte in a l6-bit word. Otherwise, AF is reset. A= 000000001111110 B= 000000000001010 - - - - - - - - - - -    =000000010011000 - - - - - - - - - - -  When we add Bit-3 of number A and B, a carry is generated into the 4th-Bit. This results is an Auxilary Carry and the AC flag get set to ‘1’. 4 Zero Flag (ZF): Zero Flag (ZF) is set if the result produced by an instruction is zero. Otherwise, ZF is reset. A=+5; B= -5; when the ALU adds these numbers, the result will be zero, hence the zero flag (ZF) is set to ‘1’. 5 Sign Flag (SF): The MSB of the result is copied into SF. Thus, SF is set if the result is a negative number or reset if it is positive. A= 000000011001100 B= 111111100110000 + = 111111111111100 So we see that the 2’s complement addition of A and B result in a number whose MSB is ‘1’ that indicates that the result is negative. Thus the sign flag is set to ‘1’ 6 Overflow Flag (OF): The overflow flag is set when the most significant bit  is changed by adding two numbers with the same sign (or subtracting two numbers with opposite signs). Overflow never occurs when the sign of two addition operands are different.  overflow flag is usually generated by an exclusive or of the internal carry into and out of the sign bit. The ALU doesn't know about signed/unsigned; the ALU just does the binary math and sets the flags appropriately.  It's up to you, the programmer, to know which flag to check after the math is done. In unsigned arithmetic, watch the carry flag to detect errors, and the overflow flag tells you nothing interesting. In signed arithmetic, watch the overflow flag to detect errors and thus, the carry flag tells you nothing interesting. The other three flags are control flags. These three flags provide control functions of the 8086 as follows: 1 Trap Flag (TF): If TF is set, the 8086 goes into the single-step mode of operation. 2 Interrupt Flag (IF): The IF controls the operation of the INTR (interrupt request) input pin If IF=1, the INTR pin is enabled; If IF=0, the INTR pin is disabled. The state of IF bit is controlled by the STI (set IF) and CLI (clear IF) instructions. 3 Direction Flag (DF): The direction flag select either the increment or decrement mode for the DI and/or SI registers during string instructions. If D=1, the registers are automatically decremented; if D=0, these registers are automatically incremented. The DF is set with STD (set direction)) and cleared with CLD (clear direction) instructions. The direction can be set for the string operations.

(b) Write short note on index and the pointer register of 8086 microprocessorclick here to see solution:
Ans:
The 8086 microprocessor has five registers which are known as the pointer and the index registers. These are:
(i) Pointer registers: BP, SP, IP
(ii) Index Registers: SI, DI
These are explained below:
(i). Pointer Registers:
• Stack Pointer (SP) is a 16-bit register pointing to program stack, ie it is used to hold the address of the top of stack. The stack is maintained as a LIFO with its bottom at the start of the stack segment (specified by the SS segment register).Unlike the SP register, the BP can be used to specify the offset of other program segments. • Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually used by subroutines to locate variables that were passed on the stack by a calling program. BP register is usually used for based, based indexed or register indirect addressing.
• Instruction Pointer: It is also a 16-bit register. It is used to hold the address of the code segment part of the memory. The physical address of the instruction is found as: Physical Address= Code Segment Register content x (10)h + Content of the Instruction Pointer
(ii). Index Registers:
• Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Used in conjunction with the DS register to point to data locations in the data segment.
• Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in string operations. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. In short, Destination Index and SI Source Index registers are used to hold address.
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