8051 Unconditional Branch Instruction

8051 Unconditional Branch Instruction

JMP

It is unconditional instruction;

jump address to next instruction is:   PC = A+DPTR

Neither the accumulator nor the DPTR register are altered. No flags are affected by this instruction.

Format Opcode/ Encoding 2nd Byte of Op-Code example  / Operation Flags affected
JMP @A+DPTR 01110011 JMP @A+DPTR

PC=A+DPTR

none

AJMP

It is also unconditional jump instruction. The destination address must be located in the same 2KByte block of program memory as the opcode following the AJMP instruction

 

Jump address = 5 high-order bits of the address of the following instruction (A15-11), the 3 high-order bits of the opcode (for A10-A8), and the second byte of the instruction (for A7-A0).

 

No flags are affected.

Format example Operation Opcode/Encoding Flags affected Byte Cycles
AJMP addr11 AJMP label PC=PC+2
PC10-0=A10-0
A10-800001, A7-0 none 2 2

 

Example:

Jump address in the program= 5 high-order bits of the address of the following instruction (A15-11), the 3 high-order bits of the opcode (for A10-A8), and the second byte of the instruction (for A7-A0).

= 00000|010|11111111

 

Address Op-Code Label Mnemonic Remarks
ORG 0
0 MOV A, #25h A=25
2    A10-8 00001

= 01000001, 11111111

PC=00000A10-0

PC=0000001011111111

AJMP NEXT A10-0=02FF = 01011111111

Opcode = A10-800001=01000001 Jump Address=A15-11of next instruction | 01011111111

 

4 79 55h

(0111100101010101)

MOV R1, 55h
     
     
02FF   NEXT: CPL A  

 LJMP

The LJMP Address = Specified 16-bit address. Jumps anywhere within 64K memory

PC=A15-0 of specified address in 2nd and 3rd byte of instruction.

.

Format                Opcode / Encoding

1st Opcode Byte    2nd and 3rd Byte Opcode

example / Operation Flags affected
LJMP addr16 00000010 A15-8, A7-0 LJMP label

PC=Addr16

none

RET

It is used to return from a subroutine

POPs  the saved address from stack and load in PC. Twice read, each time stack pointer decremented

Program execution resumes from the resulting address which is typically the instruction following an ACALL or LCALL instruction.

Format Opcode/ Encoding 2nd byte Example/ Operation Flags affected
RET 00100010 RET

PC15-8=(SP)
SP=SP-1
PC7-0=(SP)
SP=SP-1

none

 

RETI

This instruction is the end of an interrupt service routine(ISR).and execution returns immediately after the point at which the interrupt was detected

  • PC=Address POPed from stack top two locations
  • It restores the interrupt logic to accept additional interrupts.
  • No other registers are affected by this instruction.

NOTE: The RETI instruction does not restore the PSW to its value before the interrupt. The interrupt service routine must save and restore the PSW.

If another interrupt was pending when the RETI instruction is executed, one instruction at the return address is executed before the pending interrupt is processed.

 

format Opcode/ Encoding Subsequent Byte of Opcode example /Operation Flags affected
RETI 00110010  (32h) RETI

PC15-8=(SP)
SP=SP-1
PC7-0=(SP)
SP=SP-1

none

 

Updated: June 10, 2019 — 3:20 pm

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