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8085 Memory Organization

8085 Memory Organization

8085 has 16 address lines, so it can address up to 64KB of memory. This 64KB may be one single IC or can be made using smaller memory IC.  The operations on the memory IC can be a memory read or memory write. We can connect the RD’ or WR’ lines from the microprocessor to the coprresponding RD’ and WR’ pins of the memory IC. Thses signals can also be generated by an external logic

Figure above shows the necessary signals in addition to the pins on a typical 64 Byte memory module. These signals are:

6 address lines ( because 2^6 = 64)

8 address lines to carry 8-bit of data

Control lines as RD’, WR’ and CS’ (chip select)

The memory addressing  can be of two types depending on the address lines are utilised in chip selection and addressing the memory IC. These are:

  1. Full or absolute addressing
  2. Partial addressing

 

  1. Absolute or full address decoding: In this addressing the entire address lines are used for interfacing the memory IC with 8085 microprocessor. Using this method, a maximum of 64KB of memory can be interfaces with the processor. As an example. Let us interface a 16Kbyte of memory using the absolute addressing

2. Partial address decoding : This method is used when interfacing memory chip of size less than 64Kbyte. The entire address lines are not used for interfacing the memory. Some of the lines may be left unconnected hence the name partial decoding.

Address Mapping:

Address mapping is used to calculate the range of memory addresses for different memory ICs in a system. The table / map uses the chip select address lines and the actual address lines connected to the address pins of the memory IC.

Figure below shows how four memory chips of size 16 Kbytes are connected to make a total of 64Kbyte system memory. The chip select lines of each of these memory ICs are connected to the output of the 2×4 decoder. The decoder takes in the address lines A15 and A14 from the microprocessor to generate the four chip select lines.

 

Memory Map for Figure
Chip Select Address pins          Memory IC Address lines Address Range (Hex) Chip no.
15,14 13,12,11,10,9,8,7,6,5,4,3,2,1,0
0   0

0   0

0  0  0  0  0 0 0 0 0 0 0 0 0 0

1    1   1   1  1  1 1 1  1  1  1  1  1 1

0000h

3FFFh

0
0    1

0    1

0   0  0 0  0 0 0 0 0 0 0 0 0 0

1    1   1   1  1  1 1 1  1  1  1  1  1 1

4000h

7FFFh

1
1    0

1     0

0  0 0  0  0 0 0 0 0 0 0 0 0 0

1    1   1   1  1  1 1 1  1  1  1  1  1 1

8000h

BFFFh

2
1    1

1     1

0  0  0  0  0 0 0 0 0 0 0 0 0 0

1    1   1   1  1  1 1 1  1  1  1  1  1 1

C000h

FFFFh

3

 

 

 

 

 

 

 

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