8086 Internal Architecture

Introduction:

8086 is different from its predecessor 8080 and 8085 processors in the sense that the address generation, fetching the instructions from the memory are quite complex. Also 8086 contains an instruction queue of 6 bytes used for pre-fetching the instructions from the memory. Internally 8086 is divided into two logical units, these are are given in figure-1:

  1. Execution Unit: It is responsible for executing the instructions fetched from memory
  2. Bus Interface units: It is responsible for pre-fetching the instructions from the memory

The following paragraphs give a detailed discussion on these units. Figure-2 below gives the detailed architecture of the 8086 microprocessor:

Figure-2: Internal architecture 8086

 

Execution Unit

The EU consists of a the following parts:

    • General purpose Registers: AX, BX, CX and DX
    • Index Registers : SI and DI
    • Pointer Registers: BP, IP, SP
    • Flag Register : 9 flags are active these are Ov, D, I,T,S,Z,AC,P,Cy
    • ALU

The EU is where actual processing take place. The instructions from the instruction queue and the data that have been fetched by the BIU are accepted by EU and operate on the data as per the instructions. After an operation the processed data (result) can be taken to memory or other peripheral device for later use. As stated above it has 4 components: Control circuitry, ALU, Flag registers and general purpose registers. The basic functions of these different components are:

    • Control Circuits: it directs all the internal operations.
    • ALU: It is where all logic and arithmetic operations are performed.
    • General purpose registers: They are used to store data during execution.
    • Flag registers: It has a 16-bit flag register containing 9 flags that are set for certain conditions during any operation

Bus interface unit (BIU):

The basic purpose of this unit is to generate the address of the instructions and the data. It provides a full 16 bit bidirectional data bus and 20 bit address bus (i.e. Address/Data bus is de-multiplexed here). The BIU is responsible for the fetching of the data and instructions from the memory. It contains the following components.

      • Segment registers: There are four segment register namely code segment register(CS), data segment register, extra segment register, stack segment register.These register contain the 16 bit segment beginning address. The full 20 bit address is however obtained by multiplying segment register value by (10)hex and adding the offset/(instruction pointer value)
      • Multiplier/adder circuit: The BIU contain a multiplier/ adder unit for calculation of the instruction/data address.
      • Instruction Pointer: The instruction pointer points to the address of the instruction. It is a 16 bit address and thus can point to the 64KB address within a segment.
      • Queue : 8086 has a 6 byte queue, use of the queue allows pre-fetching of instruction from the memory while the execution of previous instruction is going on in the execution unit.

How does the use of BIU speedup of operations of 8086: The use of BIU helps speed up of the 8086. It is done in two different ways:

        • By pre-fetching the instructions in the instruction queue.
        • BIU allows the EU to concentrate on execution of the instructions, by taking care of the bus control functions in advance. These functions may include the address calculations etc.

Specifically BIU carries out the following two operations:

        • Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
        • The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture

FETCH AND EXECUTE OPERATION of 8086 :

Although the 8086/88 still functions as a stored program computer, organization of the CPU into a separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what happens when the 8086 or 8088 is first started.

    • The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU.
    • Register IP is incremented by 1 to prepare for the next instruction fetch.
    • Once inside the BIU, the instruction is passed to the queue. This is a first-in, first-out storage register sometimes likened to a “pipeline”.
    • Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution.
    • While the EU is executing this instruction, the BIU proceeds to fetch a new instruction. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction.

Question based on Functional Unit of 8086

  1. Draw and the functional block of the 8086.
  2. Draw and explain the functional block of the 8086
  3. Explain the function of the BIU of 8086
  4. How does the 8086 operation get speed-up
  5. What are the basic operations are carried out inside the BIU.
  6. What are the basic operations are carried out inside the Execution Unit (EU)
Updated: September 16, 2020 — 10:20 am

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