Intel 8086 a 16-bit microprocessor was introduced in year 1978. It was source code compatible with its predecessor 8080 and 8085 microprocessors. It was the first microprocessor that was part of a big breakthrough in the era of computing and was used as a main processor in PCXT personnel computers. It was developed using very large scale transistors and used approximately 29000 transistors. It has a number of added functionality as compared to 8080 and 8085 microprocessor making it to perform advanced and very complex activities. It is rich in terms of addressing, number and type of instruction, functionality by supporting single processor mode or multiprocessor communication.
Table-1 below summarizes the difference between 8085 and 8086 microprocessor.
8085 Vs 8086 Microprocessor
|sl||8085 Microprocessor||8086 Microprocessor|
|02||It is 8 bit microprocessor used about 2500 Transistors||It is 16 bit microprocessor, used about 29000 Transistors|
|03||It has 8 multiplexed address/data lines AD7-AD0||It has 16 multiplexed address/data lines AD15 -AD0|
|04||It has 16 bit address line A15 – A0, supporting 64KB of memory||It has 20 bit address line A19 – A0, supporting 1 MB of memory|
|05||It has 8 bit data bus, so it requires two accesses to data for 16 bit processing||It has 16 bit data bus. So, it require single access to process 16-bit data.|
|06||clock speed of 8085 microprocessor is 3 MHz||8086 microprocessor come with different clock speed i.e. 5,8 and 10 MHz for different versions.|
|07||It has 5 flags. (S,Z,AC,P,CY)||It has 9 flags i.e. I, D, T, OV, S,Z,AC,P,CY|
|08||Doesn’t have any concept of queue and pipelining.||It supports pipelining. It has a 6-byte queue|
|09||It operates on clock cycle with 50% duty cycle||It operates on clock cycle with 33% duty cycle.|
|10||8085 microprocessor does not support memory segmentation.||8086 microprocessor supports memory segmentation.|
|11||It has less number of transistors compare to 8086 microprocessor. It is about 6500 in size.||It has more number of transistors compare to 8085 microprocessor. It is about 29000 in size.|
|12||It is accumulator based processor.||It is general purpose register based processor.|
|13||It has only one unit which does both instruction execution and data fetching in a sequential process||It has a separate execution and bus interface unit responsible for execution and fetching the instruction and data respectively|
|14||It has no minimum or maximum mode.||It supports minimum and maximum modes of operations.|
|15||It has five interrupt lines TRAP, RST7.5, RST6.5, RST5.5 and INTR line||It has only two interrupt lines NMI and INTR|
|16||In 8085, only one processor is used.||In 8086, more than one processor is used. Additional external processor can also be employed.|
|17||In this microprocessor type, only 64 KB memory is used.||In this microprocessor type, 1 MB memory|
|18||Does not support multiplication and division instructions||Supports signed/unsigned multiplication and division instructions|
|19||There is no string manipulating instructions||String manipulating instructions to move, compare, store, scan for byte and word operations are available|
|20||Few status and machine control instruction (CLC, STC, HLT)||Large number of status control instruction such as CLC, STC, CMC, CLD, STD, CLI, STI, HLT, WAIT, LOCK etc)|
|21||There is no LOOP instruction. LOOP is executed by DCR Reg/DCX RegPair and Jump instruction with condition||It has a LOOP instruction which does the job of Decrement and Jump if-not-zero|
The 40-pins are defined in following two tables : (i) for minimum mode configuration (ii) Maximum mode configuration
|Type of Signal||Pin(s)||Symbol||Input/
|Power||40||Vcc||Supply voltage ±5V ±10%|
|Address/Data||2-16||AD14-ADO||I/O-3||Output address during the first part of the bus cycle and inputs or outputs data during the remaining part of the bus cycle.|
|39||AD15||I/0-3||Same as AD14-AD0|
|A16/S3, A17/S4, A18/S5, A19/S6||O||ADDRESS/STATUS: During T1 these are the four most significant A18/S5, address lines for memory operations. During I/O operations these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, TW, T4. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. A17/S4 and A16/S3 are encoded as shown. This information indicates which relocation register is presently being used for data accessing.
|34||BHE/s7||0-3||If 0 during first of bus cycle this pin indicates that at least one byte of the current transfer is to be made on pins AD15-AD8 if 1 the transfer is made on AD7-AD0. Status s7 is output during the latter part of bus assigned a meaning
|Interrupt||17||NMI||I||Nonmaskable interrupt request level triggered|
|18||INTR||I||Maskable interrupt request level triggered|
|19||CLK||I||Generates clock signals that synchronize the operation of processor.|
|Control Signal||21||RESET||I||Terminates activity, clears PSW, IP, DS,SS,ES, and the instruction queue, and sets
CS to FFFF; IP to 0000H; SS to 0000H; DS to 0000H; PSW to 0000H. Processing begins at FFFFO when signal is dropped. Signal must be 1 for at least 4 clock cycles.
|22||READY||I||Acknowledgment from memory or I/O interface that CPU can complete the current bus cycle.|
|23||TEST||I||Used in conjunction with the WAIT instruction in multiprocessing environments. A WAIT instruction will cause the CPU to idle, except for processing interrupts, until a 0 is applied to this pin see chp-11|
|32||RD||0-3||Indicates a memory or I/O read is to be performed|
|33||MN/MX’||I||MN/MX’=1 CPU is in minimum mode
MN/MX’=0 CPU in maximum mode
The signal on this pin redefines the meaning of pin 24-31 as described below:
The PIN definitions for minimum and maximum modes are described below:
|Minimum Mode||Maximum Mode|
|HOLD Receives bus request from BUS masters. Once granted 8086 will not gain control until this signal is dropped.
HLDA Gives a high signal to acknowledgement to requesting bus master. Pins with tristate logic are put into high impedance while HLDA is high.
|RQ/GT0,RQ/GT1||I/O||REQUEST/GRANT:RQ/GT pins are used by other local bus masters to force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and may be left unconnected.|
|29||WR’||O||In MN mode this pin is used to send a low active write (WR’) signal for writing the data on memory or IO devices depending on M/IO’ signal.||LOCK’||O||In MX Mode,LOCK output indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW.|
|For Minimum mode:
Pin 26 is DEN’ used to inform transceiver that CPU is ready to send or receive data.
Pin 27 is DT/R’ used to transmit or receive depending on High or low on this pin.
Pin 28 M/IO’Distinguishes a memory transfer from i/o transfer.
Indicate the type of transfer to take place during the current bus cycle.
|25||ALE||O||Address Latch Enable(ALE) pin is used as chip select signal for address latch to de-multiplex the AD15-AD0 lines||QS0 / QS1||O||These two pint together indicate the type of activity in the instruction queue. Table below enumerates the queue operation
|24||INTA’||O||When low this pin indicates the recognition of the interrupt by 8086 processor. The processor will generate two consecutive low pulses to the interface, first low to inform that interrupt has been recognized and the second low pulse to ask the interface to send its interrupt type over the data bus|