## Arithmetic Micro-operations

Arithmetic

 Micro-operation RTL notation description Addition R3 <– R1 + R2 Content of R1 and R2 added, result in R3 Subtraction R3 <– R1 – R2 Content of R2 subtracted from content of R1 added, result in R3 1’s complement R2  <–  R2’ Content of R2 complemented 2’s complement R2  <– R2’ +1 2’s complement on the Content of R2 Subtraction using 2’s complement R3  <– R1 + R2’ + 1 Subtraction using 2’s complement Increment R1   <–  R1+1 An increment micro-operation Decrement R1   <–  R1 – 1 A decrement micro-operation

We now describe the arithmetic circuits for performing the above arithmetic micro-operations. A Half adder and full adders are the basic building blocks used in above operation.

A half adder is an arithmetic circuit used to add two binary bits. These bits are carry-in and a bit of the number. The symbolic notation of the circuit is shown below:

It finds applications as an incrementer and decrmenter.

Now, RTL is used to generate the circuit from the symbolic code of RTL. For example when the following RTL code is written, the circuit shown in figure … will be generated.

S <= A xor Cin

C <= A and Cin

Now, if the register ‘A’ is assumed to be a 4-bit register, the other input to act as a carry-in to the least significant bit will be equivalent to:

The circuit of Fig-1 can be extended to an n-bit binary incrementer by extending the diagram to include n half-adders. The least significant bit must have one input connected to logic-1. The other inputs receive the number to be incremented or the carry from the previous stage.

A full adder can be used for implementing the n-bit binary adder. In the following example, two 4-bit numbers A(3-0) and B(3-0) are taken as input to the four full adders. To add the number A and B, Cin input is connected to ground or ‘0’ logic values. The carry out of 1st stage FA is connected as Carry-in to the 2nd stage FA, and carry out of 1st stage FA is connected as Carry-in to the 2nd stage FA, and so on. The carry out of the most significant FA is the final carry out.

S(3-0) = A(3-0) + B(3-0)

C4  is the final carry-out of the most significant FA  = A3.B3 + (A3 xor B3).C3

The circuit of figure-2 can be expanded to perform 2’s complement addition-subtraction. We use an XOR gate to perform the 2’s complement of a number. The operation is shown in figure-3

The output of the XOR is same as B when M=0, and Y is 1’s complement of B when M=1. We can easily get the 2’s complement of B by adding ‘1’ to its 1’s complement. This logic is incorporated in the binary adder circuit described earlier to get the 2’s complement adder-subtracter circuit shown in figure-3

When M=0, the B input is passed directly as one of the input to the FA and also the carry-in which is same as M  is zero (‘0’). The output thus obtained will be the binary addition of A and B.

Binary subtraction: When M=1, XOR performs the 1’s complement of B and also the Carry-in, which is same as M becomes ‘1’. This results in subtraction using 2’s complement arithmetic. The operation is S= A + B’ +1

Arithmetic Unit

All the operations discussed above can be implemented in a single composite circuit shown in figure-5. The circuit uses four FA. One of the input A is connected directly to one input of FA, the 2nd input is connected though the MUX. By controlling the data inputs to the adder, it is possible to obtain different types of arithmetic operations.