ASSERT Statement in VHDL


ASSERT Statement

ASSERT statement is used to display message of some types that may be generated by the system when a certain condition such as a fault occur in the system. Thus, it serves as an exeption handling instruction within a program and is most often used for test purposes. Assertion can be used to terminate the execution of a simulation upon a pre-defined fault class.

For this a condition is defined, which should be fulfilled in normal operation mode. If this is not the case a fault message may be generated.

Syntax of ASSERT statement is:

assertion statement ::= [ label : ] assertion ;

assertion ::=

ASSERT condition

[ REPORT expression ]

[ SEVERITY expression ];

User defined text messages are may be printed with the help of REPORT expression when the ASSERT condition evaluates to false.

The expression following the SEVERITY statement must have the type severity_level and defines the fault class which may be note, warning, error and failure. If the SEVERITY statement in the ASSERT statement is omitted, error is by default classified.

REPORT Statement

The VHDL-93 standard defines a report statement, by which means reports may be printed without the use of the ASSERT statement. The syntax is:

report_statement ::= [ label : ] RETURN expression

[ SEVERITY expression ] ;

Example: the use of the assert and report statement is illustrated in the following halfAdder and its test bench that follows the VHDL code of halfAdder

library ieee;

use ieee.std_logic_1164.all;

entity halfAdder is

port( A, B : in std_logic;

sum, Cout : out std_logic);

end halfAdder;

architecture dataflow of halfadder is

begin

sum <= A xor B;

Cout <= A and B;

End;

—————————————————————

Test bench for half adder

library ieee;

use ieee.std_logic_1164.all;

entity halfAdder_tb is

end halfAdder_tb;

architecture tb of halfAdder_tb is

component halfAdder is

port(

A, B : in std_logic;

sum, Cout : out std_logic

);

end component;

signal A, B, sum, Cout: std_logic;

begin

mapping: halfAdder port map(A, B, sum, Cout);

process

variable errCnt : integer := 0;

begin

–TEST 1

A <= ‘0’;

B <= ‘1’;

wait for 10 ns;

assert(sum = ‘1’) report “sum error 1” severity error;  — report if condition is false

assert(Cout = ‘0’) report “Cout error 1” severity error; — report if condition is false

if(sum /= ‘1’ or Cout /= ‘0’) then

errCnt := errCnt + 1;

end if;

–TEST 2

A <= ‘1’;

B <= ‘1’;

wait for 10 ns;

assert(sum = ‘0’) report “sum error 2” severity error;

assert(Cout = ‘1’) report “Cout error 2” severity error;

if(sum /= ‘0’ or Cout /= ‘1’) then

errCnt := errCnt + 1;

end if;

–TEST 3

A <= ‘1’;

B <= ‘0’;

wait for 10 ns;

assert(sum = ‘1’) report “sum error 3” severity error;

assert(Cout = ‘0’) report “Cout error 3” severity error;

if(sum /= ‘1’ or Cout /= ‘0’) then

errCnt := errCnt + 1;

end if;

—- SUMMARY —-

if(errCnt = 0) then

assert false report “Success!” severity note;

else

assert false report “Faillure!” severity note;

end if;

end process;

end tb;

Self Practice Questions

  • What is assertion statement, explain briefly its use.

  • Write short note on Report statement in VHDL

  • Explain delay and their effect on signal drivers.

  • Write short note on multiple processes and postponed processes.

  • What is the resolution function? Explain briefly.

error: Content is protected !!