Bus and memory transfer:
Figure-6 shows the general internal architecture of a hypothetic CPU and its interfacing to a memory unit. All internal and external operations take place over a set of wires called as “System Bus”. The system bus can be organized in a number of ways. These are:
- System bus using multiplexers
- System bus using tri-state buffers
System bus using multiplexers
This is more common type of system bus. The source registers bits are selected by multiplexers and the multiplexer outputs are connected onto the data bus. A bus system for transferring word size of four-bits (4-bit registers) is shown in figure-1. Here the content of the register which is 4-bit is transferred onto the bus.
We use four multiplexers of size 4×1 with common select lines for transferring the four bits of a registers. As seen in figure, when control signal S1S0=00, all the multiplexers select one of the input from the same register i.e. register-A.
Operational table for register transfer onto a common bus
|Select line of MUX||Register Selected for inputs||MUX line selected in All MUXes||Content transferred on 4-bit common Bus|
|00||Register A||First input of all MUX||A3A2A1A0|
|01||Register B||2nd input of all MUX||B3B2B1B0|
|10||Register C||3rd input of all MUX||C3C2C1C0|
|11||Register D||4th input of all MUX||D3D2D1D0|
The transfer of information from some source register to a destination register is performed by transferring the content of the register to the bus and then the contents of the bus to a destination register. This can be can be accomplished by connecting the bus lines to the inputs of all destination registers and activating the load control of the desired destination register. The symbolic notation for this operation is shown as:
BUS <– C, R1 <– Bus
or simply as:
R1 <– C
The number of multiplexers needed to construct the bus is equal to n, the number of bits in each register. The size of each multiplexer must be k x 1 since it multiplexes k data lines
- So number of MUX = No. of bits in each Registers
- Size of MUX = Number of data lines it multiplexes
The CPU reads the instruction from the Memory decodes it and generates necessary timing
We have learnt that a logic gate exhibit two binary states these are logic ‘0’ and logic ‘1’. A tri-state or three-state gate is a digital circuit that exhibits three states. Two same as that in logic gates and the third state is high impedance state. The high-impedance state behaves like an open circuit, which means that the output is disconnected and does not have a logic significance. The logic symbol for a tri-state buffer is shown in figure-2 below:
A tri-state buffer can be used as a 1-bit bus line . When the control input is ‘0’, the buffer is in high impedance or OFF and the input then is blocked from appearing on the output.
We can us multiple sources to be commented to the bus line by use of decider. Figure-3 shows four buffers connected to one single using a decider,
Bus line with Tri-State-buffers.
Here, in figure-4 we expand the concept of figure-3 to construct a 2-line bus using tri-state buffers. Two decoders are used for transferring the two-bit contents of the registers in to the bus, more are required flor two-but transfer four such decoders will be required for four bit transfer
We can expand this circuit by connecting two more decoders and rewiring for making bus size as four-bit. The operation then is described by the following truth table.
|Decoder Select Line (S1S0)||Decoder Bit Selected for Bus transfer||Register number and the bits selected for transfer|
|00||Bit-0 of all decoders||Register-A
|01||Bit-1 of all decoders||Register-B
|10||Bit-2 of all decoders||Register-C
|11||Bit-3 of all decoders||Register-D
The memory unit uses additional control signals. These are chip select, memory read, memory write. When a read operation is performed, the data from a specific address given in address register is loaded into the data register. Similarly, for a write operating, the data from the data register is transferred at the location given in address register.