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Digital Design using VHDL

Iteration (LOOP) Statement in VHDL

by Ravinder Nath Rajotiya - 0

Loop statements are a catagory of control structures that allow you to specify repeating sequences of behavior in a circuit. The statement are used for iterating a well-defined task. In each iteration it then increaments or decrement some local identifier for use inside the LOOP statement. VHDL has following types of iterative statements i. FOR statement ii. WHILE statement iii. and infinite loops Syntax for the iteration statements: i. FOR statement [label :] FOR index in <range> LOOP Statement(s); End LOOP; Example-1: Synthesize a 4-bit Incrementer in sequential modelling in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity incrementer is generic(N: integer:=6); port ( a : in STD_LOGIC_VECTOR (N downto 0); b : out STD_LOGIC_VECTOR (N downto 0) ); end incrementer; architecture Behavioral of incrementer is begin process(a) variable x: std_logic_vector(N downto 0); begin b(0) <= NOT

ASSERT Statement in VHDL

by Ravinder Nath Rajotiya - 0

ASSERT Statement ASSERT statement is used to display message of some types that may be generated by the system when a certain condition such as a fault occur in the system. Thus, it serves as an exeption handling instruction within a program and is most often used for test purposes. Assertion can be used to terminate the execution of a simulation upon a pre-defined fault class. For this a condition is defined, which should be fulfilled in normal operation mode. If this is not the case a fault message may be generated. Syntax of ASSERT statement is: assertion statement ::= [ label : ] assertion ; assertion ::= ASSERT condition [ REPORT expression ] [ SEVERITY expression ]; User defined text messages are

Sequential Statements (if, case, NULL) in VHDL

by Ravinder Nath Rajotiya - 0

The sequential constructs refer to the VHDL language constructs that execute in sequence. The different sequential constructs are : Wait statement If statement Case statement Loop statement Null statement Next statement Assertion statement Report statement Procedure call statement Return statement we now discuss all these sequential statements in the  following paragraph : IF statement: The IF statement used to transfer the control of the program to another set of sequential statement based on the value of the condition in the expression that evaluates to BOOLEAN value. The syntax of the IF statement is: Format-1 Format-2 Format-3 IF expression then Statement(s); ELSE Statement(s) END IF IF expression then Statement(s); ELSIF expression then Statement(s) -- END IF IF expression then IF expression then IF expression then Statement(s); ELSE Statement(s) End if; End if; End if; The following example illustrates the use of if

Sequential Style Modeling

by Ravinder Nath Rajotiya - 0

Sequential style of modeling is also called the behavioral style. This style of coding make use of the process statement(s). Once an entity is declared, the a process is defined inside the architecture. Sequential code inside the process allows statements like IF, CASE, LOOP and WAIT and the desired operators inside the code.The general structure of a behavioural style modelling in VHDL is given below: LIBRARY <library_name>; USE library_name.<package_name>.all; ENTITY <entity_name> IS PORT( Signal_name(s) : mode type ; Signal_name : mode type ); END [ENTITY] [entity_name] ; ARCHITECTURE behavioural OF<entity_name> IS --declaration of signal, constant, type; BEGIN --concurrent statement --[process_label :] PROCESS [(sensitivity list)] --variable, constant declarations; BEGIN Sequential_statement(s); End PROCESS[process_label ]; END [Architecture] [behavioural]; As seen in the above prototype VHDL code, a sequantial code need a process statement. To make the code  sequential,te statements have to be

Operator Overloading in VHDL

by Ravinder Nath Rajotiya - 0

At times, the coder need to use the same operator for processing objects of different type. For example, VHDL has a predefined operator '+'  to add two integers, what is we add two characters, add two real values, add two strings, add two vectors and so on. VHDL and any other language do not have seperate operator for those purpose and thus would demand for a separate operator. As the number of operators increase it’ll be hard to remember them. Definition Overloading allows the coder to write separate subprograms for the same object (operator) to perform on values of different types. An operator is overloaded by defining a functionality other than its pre-defined meaning. This is done by defining a function and the

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