Sequential-Synchronous Counter Design The different steps for the design of the synchronous sequential counter circuits are: i)          State diagram ii)         state table and  excitation table iii)        Simplification using K-Map iv)         Logic Design Number of Flip-Flops required for implementing a counter: For N-bit counter, N flip-flops would be required For counter counting upto  N states, the number of flip-flops required would be :                                              No._of_FFs = Log2 N  = Log2 2n Let us now start with the design problems.   Example-1: Design a 4-bit synchronous up counter using T flip-flops Step-2: The Excitation Table State Excitation PS NS T1 T2 T3 T4 0000 0001 0 0 0 1 0001 0010 0 0 1 1 0010 0011 0 0 0 1 0011 0100 0 1 1 1 0100 0101 0 0 0 1 0101 0110 0 0 1 1 0110 0111 0 0 0 1 0111 1000 1 1 1 1 1000 1001 0 0 0 1 1001 1010 0 0 1 1 1010 1011 0 0 0 1 1011 1100 0 1 1 1 1100 1101 0 0 0 1 1101 1110 0 0 1 1 1110 1111 0 0 0 1 1111 0000 1 1 1 1   Step-3: Logic Equations for Inputs T1        =          Q1’Q2Q3Q4  +  Q1Q2Q3Q4 T2        =          Q1’Q2’Q3Q4 + Q1’Q2Q3Q4 + Q1Q2Q3Q4 + Q1Q2’Q3Q4 T3       

Introduction In the previous lectures, you have learnt the Boolean algebra and K-Map methods of solving Boolean expressions. These methods are simple and easy for less number of variables say upto four. But for more than 4 variable equations, these become tedious. So, another method known as Quine Mc-Clusky or Tabulation Method is used for solving Boolean expression involving four or more variables. Quine Mc-Clusky or Tabulation Method This is again a simple method but requires lot of concentration while looking for minterms with 1-bit change. A little distraction of mind will lead to committing a mistake. Various steps involved in simplification are: Preparing index value based on number of 1’s in the minterms of the equation including don’t care terms. Rearranging the minterms as

Magnitude Comparator: A magnitude comparator is a combinational circuit that compares two binary numbers and determines their relative magnitude. The schematic block diagram in figure-1 has two inputs and three outputs. It compares two numbers for equality, less than and greater than conditions. Depending on the comparison, one of the output will be true and the others will be false.   The table-1 gives the function of the two 1-bit magnitude comparison. A B  GT   (A>B) LT   (A<B) EQ    (A=B) 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 AB' A'B A'B' + AB= (A ⊙ B) The logic equations for the three output are: GT  =  AB’ LT   =  A’B EQ  = A’B' + AB = A  ⊙   B Figure-2: 1-bit magnitude comparator 2-bit Comparator This type of comparator is used to compare two numbers of 2-bits each. The table below shows the comparison. Functional table for two

Implementing with Decoders: A decoder is a combinational circuit that converts N-bit binary information to 2N unique output lines. It is able to represent upto 2N distinct elements of coded information. General type decoders usually come in sizes of Nx2N where N is the number of input lines. With a given input, only one of the 2N  output is active.   Applications of decoders: Decoders find numerous applications in : BCD to 7-segmanet decoders BCD to Decimal Decoder Memory address decoders Instruction decoders In Display devices 2 to 4 Line Decoder A 2 to 4 line decoder has 2 input lines, and 4 output lines. A decoder may also have an Enable (EN input) to enable or disable it. Enable Input Selection Lines Output Lines EN S1 S0 O0 O1 O2 O3 1 0 0 1       S1' S0' 0 0 0 1 0 1 0 1    S1' S0 0 0 1 1 0 0 0 1     S1 S0' 0 1 1 1 0 0 0 1