8051 Conditional Branch Instructions 8051 Micro-controller by Ravinder Nath Rajotiya - April 23, 2019May 10, 20210 CONDITIONAL BRANCH INSTRUCTIONS CJNE The CJNE instruction compares the first two operands and branches to the specified destination if their values are not equal. If the values are the same, execution continues with the next instruction. format example Operation Opcode/ Encoding Flags affected Byte Cycles CJNE @Rn, #immd,offset CJNE @R1, #24h,label PC=PC+3 If (Rn) <>#data PC=PC+offset If(Rn) <#data C=1 Else C=0 1011011n, #imm 8-bit, offset C 3 2 CJNE A, #data, offset CJNE A, #01h, label PC=PC+3 If A <> #immd PC=PC+offset If A<#immd C=1 Else C=0 10110100, #immd, offset C 3 2 CJNE A, direct, offset CJNE A, 60h, label PC=PC+3 If A<> (direct) PC=PC+offset If A < (direct) C=1 Else C=0 10110101, direct 8-bit adder, offset C 3 2 CJNE Rn, #immd, offset CJNE R6, #12h, label PC=PC+3 If Rn <> immediate PC=PC + offset If Rn < immd C=1 Else C=0 10111nnn, #immd 8-bit, offset C 3 2 DJNZ The DJNZ instruction decrements the byte indicated by the first operand and, if the resulting value is not zero, branches to the address specified in the second operand. format example Operation Opcode/ Encoding Flags affected Byte Cycles DJNZ direct, offset DJNZ 40h,label PC PC+2 (direct)=(direct)-1 If
8051 Unconditional Branch Instruction 8051 Micro-controller by Ravinder Nath Rajotiya - April 23, 2019May 10, 20210 8051 Unconditional Branch Instruction JMP It is unconditional instruction; jump address to next instruction is: PC = A+DPTR Neither the accumulator nor the DPTR register are altered. No flags are affected by this instruction. Format Opcode/ Encoding 2nd Byte of Op-Code example / Operation Flags affected JMP @A+DPTR 01110011 -- JMP @A+DPTR PC=A+DPTR none AJMP It is also unconditional jump instruction. The destination address must be located in the same 2KByte block of program memory as the opcode following the AJMP instruction Jump address = 5 high-order bits of the address of the following instruction (A15-11), the 3 high-order bits of the opcode (for A10-A8), and the second byte of the instruction (for A7-A0). No flags are affected. Format example Operation Opcode/Encoding Flags affected Byte Cycles AJMP addr11 AJMP label PC=PC+2 PC10-0=A10-0 A10-800001, A7-0 none 2 2 Example: Jump address in the program= 5 high-order bits of the address of the following instruction (A15-11), the 3 high-order
Subroutine Call and Return Instructions 8051 Micro-controller by Ravinder Nath Rajotiya - April 23, 2019June 10, 20190 Branch Type Instructions These are of two types: Subroutine CALL Instruction JMP Instruction Unconditional JMP Conditional JMP Subroutine Call Instructions: These instructions are used to calls a subroutine located at the specified address. There are two subroutine Call instructions, theses are ACAL and LCALL instruction ACALL Instruction Size : Two bytes Requirement : Subroutine that is called must be located in the same 2KByte block of program memory as the opcode following the ACALLinstruction. Operation: PC is first incemented twice to obtain the address of the following instruction PC is saved on stack low-byte first and high byte at high address. SP increased by two. Calcultes the subroutine address as: by combining the 5 high-order bits of the incremented PC (for A15-A11), the 3 high-order bits
8051 Arithmetic Instructions 8051 Micro-controller by Ravinder Nath Rajotiya - April 22, 2019June 10, 20190 Arithmetic Instructions One of the operand in arithmetic type of instruction is accumulator. Other operand, if there, will be immediate value, direct memory, register, register indirect, except in case of MUL and DIV where register B is used to hold the value of the 2nd operand. ADD Format of Instruction Opcode/Encoding Example and Operation Flags Affected ADD A, #imm 00100100 Immediate 8-bit ADD A, #03h A=A+#data C,AC,OV,P ADD A, @Ri 0010011i (i is Reg number) -- ADD A, @R1 A=A+ (Ri) C,AC,OV,P ADD A, direct 00100101 Direct ADD A, 20H A=A+(20) C,AC,OV,P ADD A, Rn 00101nnn -- ADD A, R0 A=A+R0 C,AC,OV,P ADDC Format of Instruction Opcode/Encoding Example and Operation Flags Affected ADDC A, #imm 00110100 #immediate ADDC A, #43h C,AC,OV,P ADD A, @Ri 0011011i (i is Reg number) -- ADDC A, @R1 C,AC,OV,P ADD A, direct 00110101 Direct ADDC A, 20H C,AC,OV,P ADD A, Rn 00111nnn -- ADDC A, R0 C,AC,OV,P Write a program to add multiple byte of data in assembly language of 8051 MOV R1, 55h ; Mov value at address 55h to R1 MOV
8051 Data Transfer Instructions 8051 Micro-controller by Ravinder Nath Rajotiya - April 22, 2019June 10, 20190 Date Transfer Instructions Used to move a source data to destination MOV Instruction Instruction/Addressing Opcode Subsequent Byte Example and Operation Flags Affected MOV Rn, #immediate 01111nnn MOV R4, #5h None MOV A, #Immediate 01110100 Immediate MOV A, #0FFh P MOV @Rn, #immediate 0111011n Immediate MOV @R0, #05h None MOV direct, #immediate 01110101 Direct, Immediate MOV P2, #0FFh None MOV Rn, A 11111nnn MOV R5, A None MOV A, Rn 11101nnn - MOV A, R6 P MOV @Ri, A 1111011i -- MOV @R0, A None MOV A, @Ri 1110011i -- MOV A, @Ri P MOV dest_direct, src_direct 10000101 Src_Address, dest_Addr MOV P1, P0 None MOV direct, @Rn 1000011n direct MOV P0, @R1 None MOV @Ri, Direct 1010011i direct MOV @Ri, P2 None MOV direct, A 11110101 direct MOV P0, A None MOV A, Direct 11100101 direct MOV A, P0 P MOV direct, Rn 10001nnn direct MOV P2, R5 None MOV DPTR, #immediate 10010000 immediate15-0 MOV DPTR, #1234h None MOV Rn, direct 10101nnn Direct MOV R4, P1 None MOV C, bit 10100010 bit MOV C, 22h None MOV bit, C 10010010 C MOV, 22, C None MOVC This instruction is used to move a byte from the code or program memory to the accumulator. Syntax : MOVC A, @A + PC MOVC A, @A+DPTR MOVC A, @A+DPTR 10010011 -- MOVC A, @A+DPTR A=(A+DPTR) P MOVC A, @A+PC 10000011 -- MOVC