AIM Write VHDL programs for the following circuits, check the wave forms and the hardware generated register shift register Objective: The objective of this lab is to : revise the theory behind the working of the registers To learn VHDL coding for the registers Synthesize register using VHDL Verify the operation using functional Simulation […]
Category: VHDL Lab
Design of Counters using VHDL
AIM Write a VHDL program for a counter and check the wave forms and the hardware generated Objective: Objective of this lab is to: Revise the theoretical work Learn the VHDL Coding Synthesize counters using VHDL Verify the functionality using ISIM simulator Theory: A digital counter is a sequential circuit consisting of a number of […]
Design of Flip-Flops in VHDL
AIM : Design of Flip-Flops in VHDL Objective: To revise the basic theory behind the working of the flip flops To understand the syntax of VHDL To synthesize and simulate using VHDL Theory: The theory extend from latches to flip-flops. the basic similarity and differences between a latch and a flip-flop being: Sl Latch Flip-Flop […]
Design of Code Converters in VHDL
AIM: CODE CONVERTERS IN VHDL Objective: To revise the basic theory behind the working of the Code Converters To synthesize and simulate using VHDL Theory of Code Converters: We, in our day-to-day life deal with numerous forms of data, it can be decimal digits and numbers, alphabets and string or even the special symbol e.g your […]
Design of Comparator in VHDL
AIM: Write a VHDL program for a comparator and check the wave forms and the hardware generated Objective: To understand the working of Comparator To learn VHDL codin To understand functional simulation Theory: A comparator is a combinational circuit that compares two objects and returns the outcome as “equal”, “less then”, or “greater then”. The […]
Synthesis of Encoder
Priority Encoder A priority Encoder encodes one of the many inputs but only the key having the highest priority is encoded first. If highest priority key is not pressed then the next lower priority key is encoded and so on. The functional table is given below, In the table Y0 and Y1 are the encoded […]
Synthesis of Decoders in VHDL
Decoder Design using VHDL Objective: To learn how to write VHDL code To Learn how to do functional simulation To do study of the synthesis done by VHDL and the theoretical desin obtained using algebraic solution. Requirement: A computer system installed with XILINX VHDL Theory: Theory: A decoder generally decodes a binary value into a […]
Synthesis of De-Multiplexers using VHDL
Write VHDL programs for synthesizing of DeMultiplexer Objective: To learn the VHDL coding for Demultiplexer To understand the behavior of Demultiplexer To synthesize and simulate Demultiplexer Theory: A de-multiplexer is a combinational circuit that behavior opposite to a multiplexer. It has a single input, ‘S’ control inputs and 2S as output lines. Only one of […]
Synthesis of Multiplexer
Write VHDL programs for the following circuits, check the wave forms and the hardware generated multiplexer De-Multiplexer Objective: To learn the VHDL coding for Multiplexer To understand the behavior of Multiplexer To Synthesize multi-bit MUxes To Synthesize larger MUXs using smaller MUXs To simulate Multiplexer Theory: A multiplexer is a combinational circuit which has […]
Parallel Adders
Parallel Adders Objective: To understand how FA can be cascaded to for adding multi-bit numbers. To develop VHDL code for design of VHDL Code in different style of modeling To synthesize and simulate the parallel adders Theory: A Full adder is a combinational circuit that adds two one bit numbers along with a carry from the […]
