Category: VHDL Lab

BCD Adder

AIM: To Synthesize the BCD Adder and Generate the hardware and the waveform Objective: To understand basic process of addition To understand the VHDL syntax To Synthesize the BCD adder circuit To simulate verify the result Theory: BCD numbers are represented as 4-bit code. With 4-bits, we can have 16 binary combinations of which only […]

Schematic Design Entry in VHDL

Schematic Design Entry in VHDL Open the ISE project navigator by double clicking on the icon Go to file Click new project, Type the name of the project in new project window and click next. Select device family, device, package, speed grade and design flow and click next in the design properties window. Click next […]

VHDL Program for Half Subtractor

AIM: Write VHDL programs to synthesize a Half subtractor (HS) circuit in VHDL and check the wave forms and the hardware generated Objective: To learn the VHDL coding for HS To understand the behavior of HS To synthesize and simulate HS Theory A half subtractor is a combinational circuit that produces the difference and borrow outputs […]

Design of Adder Subtractors in VHDL

AIM : To Synthesize different types of adder subtractor Objectives To understand the working of different types of adder subtractor circuits To develop VHDL code to synthesize different types of adder subtractors To simulate and analyse the different types of adder subtractors Synthesis of Adder Subtractors   Large and Complex circuit are designed using structural Modeling. […]

Design of a Full Adder in VHDL

AIM :Write a VHDL Code to design a Full adder using different modeling style Objective: To understand the operation of a Full Adder, logic equation and the truth table To develop VHDL code for design of VHDL Code in different style of modeling To synthesize and simulate the Full adder circuit Theory: A Full adder […]

VHDL Programs for Half Adder

Write VHDL programs for the following circuits, check the wave forms and the hardware generated for Half Adder Objective I. To understand the function and operation of a Half Adder ii. To learn the modeling styles of Half Adder in VHDL iii. To synthesize and simulate Half Adder Theory of a Half Adder: A half adder […]

Design all gates using VHDL

Experiment-1: AIM : Design all gates using VHDL Objectives: The objective of this experiment is to: i. To revise the working of various logic gates ii. To learn the VHDL coding iii. To simulate for functional verification iv. To implement on CPLD / FPGA Symbols and Truth Table of Logic Gates: Symbol Name Symbol Truth Table […]

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