Write a VHDL program for a counter and check the wave forms and the hardware generated
Objective of this lab is to:
- Revise the theoretical work
- Learn the VHDL Coding
- Synthesize counters using VHDL
- Verify the functionality using ISIM simulator
A digital counter is a sequential circuit consisting of a number of flip-flops connected in some suitable manner to count the sequence of pulses / events applied to it. The counter like a register is a sequential circuit.
Types of Counters
- Synchronous and Asynchronous counters
- Single and Multi-Mode Counters (Up counter, Down Counter, Up-Down Counter)
- Modulus Counter: Modulus-3, Modulus-6, Modulus-10 etc.
- Shift register counters:- Ring Counter, Johnson Counter etc.
- The single and multimode counters are used for single mode that is either up or down counter or multi-mode counter as up/down counter.
- The modulus counter on the other hand are the counters that count upto a certain count, a counter that counts 0 through 9 is Modulus-10 counter, Its name come from the number of states that it counts. So we have different modlulus counters as mudulus-3, modulus-6, modulus-10.
- Ring counters: these are applications of the shift registers and are of various types such as Ring Counter, Johnson Counter etc.
Applications of Counters:
- in counting applications.
- To measure the time interval between two unknown time instants
- To measure the frequency of a given signal
- Counters are useful for digital clocks and timers
- Used in oven timers, VCR clocks, etc
- The registers and the counters are found as a very important building block of sequential logic.
Synthesis of Counters using VHDL
Binary Up Counter
Binary up counter in VHDL
entity binary_counter is
clk : in STD_LOGIC;
reset : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0)
architecture Behavioral of binary_counter is
signal tmp : std_logic_vector(3 downto 0);
process (reset, clk)
elsif (clk’event and clk=’1′) then
tmp<= tmp + 1;
Simulation of Binary Up Counter
Binary Up-Down Counter
Binary Up-Down Counter
entity up_down_counter is
DIR, CLK: in std_logic;
count_out: out std_logic_vector(7 downto 0)
architecture Behavioral of up_down_counter is
signal count : STD_LOGIC_VECTOR (7 downto 0) := X”00″;
if (clk’Event and clk = ‘1’) then
if (DIR = ‘1’) then
count<= count + ‘1’; — counting up
elsif (DIR = ‘0’) then
count<= count – ‘1’; — counting down
count_out<= not count;