Identifiers in VHDL


Identifiers in VHDL

An identifier represent a token in VHDL. VHDL has token in the form of reserve word and user defined word. Further, identifier may be :

  • Basic identifier
  • Extended identifiers.
  1. Basic Identifiers:

These are used to define user defined names and following rules applies to the valid basic identifiers:

    1. The valid character set in The first letter of an identifier is always an alphabet (‘a’…’z’ or ‘A’…..’Z’) and digits 0 – 9.

    2. the first letter cannot be a special character or digit or underscore

    3. The last letter may be a letter or a digit but cannot be an underscore

    4. Double underscore anywhere is not permitted

    5. Graphical character/special symbols are not permitted

    6. Keywords cannot be used as basic identifiers

Examples

Valid basic Identifiers:

AND_GATE, AND2,

Invalid basic Identifiers

_gate

My_design_ — end with underscore

My_ _design — double underscore

@mydesign — starts with special character

2mydesign — starts with digit

2. Extended Identifiers

Extended identifiers are written inside the backslash.

    1. Allow the coder to use even keywords

    2. Allow special symbols, etc anywhere in naming the identifiers.

Examples of valid extended identifiers

\my_ _design\

\my\\design\

\@CPUdesign\

Examples of invalid identifiers

\my\design\

\my_design_\2

Basic identifiers

Extended identifiers.

Identifiers are used for naming all named entities in VHDL.

The extended identifiers were included in VHDL ’93 in order to cater to the requirements that cannot be met with basic identifiers. For example, if one wants to indicate an active low signal such as an active low RESET, one cannot call it /RESET. Extended identifier rules allow identifiers with any sequence of characters.

They can be of any length , but must fit on the same line in the code

 They can be of any length

Graphic character is not allowed as first character.

They may contain any graphic character (including spaces and non-ASCII characters), but placed between backslashes

Underscore is allowed inside identifier.
Underscore is not allowed as a first or last character of an identifier.
Moreover, two underscores side by side are not allowed as well

Underscore and other graphical characters are allowed Can be put, since identifier is enclosed in back slash.
Also If a backslash is to be used as one of the graphic characters of an extended literal, it must be doubled.

Not case sensitive, Upper- and lower-case letters are treated as same.

Upper- and lower-case letters are distinguished in extended literals.

Reserved words cannot be used

Reserved words are allowed

Reserved words in VHDL

The meaning of the reserved words is already predefined the language. They cannot be used or purpose other than their predefined meaning. Various keywords are given below:

ABS

DISCONNECT

IS

PACKAGE

SLA

ACCESS

DOWNTO

LABEL

PORT

SLL

AFTER

ELSE

LIBRARY

POSTPONED

SRA

ALIAS

ELSIF

LINKAGE

PROCEDURE

SRL

ALL

END

LITERAL

PROCESS

SUBTYPE

AND

ENTITY

LOOP

PROTECTED

THEN

ARCHITECTURE

EXIT

MAP

PURE

TO

ARRAY

FILE

MOD

RANGE

TRANSPORT

ASSERT

FOR

NAND

RECORD

TYPE

ATTRIBUTE

FUNCTION

NEW

REGISTER

UNAFFECTED

BEGIN

GENERTATE

NEXT

REJECT

UNITS

BLOCK

GENERIC

NOR

REM

UNTIL

BODY

GROUP

NOT

REPORT

USE

BUFFER

GUARDED

NULL

RETURN

VARIABLE

BUS

IF

OF

ROL

WAIT

CASE

IMPURE

ON

ROR

WHEN

COMPONENT

IN

OPEN

SELECT

WHILE

CONFIGURATION

INERTIAL

OR

SEVERITY

WITH

CONSTANT

INOUT

OTHERS

SHARED

XNOR

OUT

SIGNAL

XOR

Questions:

  • What are different types of libraries in VHDL write their function.

  • What do you mean by identifier in VHDL, what are their types? Write some of the valid and invalid identifier

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