L-3 Internal Architecture of 8085

Internal Architecture of 8085

The internal architecture describes various internal components that make the 8085 and their interconnect. Figure 3.1 shows the internal architecture of 8085


Different internal components of 8085 are given and described in following section:

  1. Arithmetic & Logic Unit
  2. General Purpose Registers
  3. Instruction Register (IR)
  4.  Instruction Decoding
  5. Timing and control unit
  6. Internal Bus or data path
  7. Interrupt Control unit for externally initiated signals
  8. Serial I/O Control unit
  9. Address Incremented / Decremented


  • Arithmetic & Logic Unit (ALU): 
      The purpose of ALU is to perform the arithmetic, logical, shift and comparison operations on the data and produce the result. The status of the current operation is stored in the status result which can be used in programming for decision making and for taking branch to other areas in the memory.

    1. Register File: 8085 register file consist of following registers: a) General Purpose: these registers can use used as single 8-bit registers and are – B, C, D, E, H, L. When used in pairs for 16-bit operations the they are used BC, DE, HL pairs. (b) Pointer Registers: Stack pointer (SP) to point into the stack area, program counter(PC) to point to the next instruction in memory. PSW – Accumulator and Flag register together are called PSW or program status word. Flag or program status register is a 8-bit register whose only 5-bits are used and these bits are Sign, Zero, Auxiliary Carry, Parity and Carry. These are set or reset depending on the status of the current operation in the ALU. Temporary Register- These registers W, Z are not visible to the programmer. they are used during subroutine calls and during the execution of XCHG instruction which is used to exchange content of HL with DE (H with D and L with E)
    2. Instruction Register: is a 8-bit register. During the instruction fetch operation the OPCODE fetched from memory is stored in IR register then it is transferred to instruction decoder for decoding.
    3. Instruction Decoder: After an instruction is read from the memory, it is decoded to know the OPCODE it contains so that the control unit can be requested to generate the necessary control signals for various units which are required during the execution of this instruction e.g to select the ALU for that operation, fetch the data from memory if required etc
    4. Timing and Control Unit: The purpose of the timing and control unit is to generate the necessary timing synchronization and control signals so that the required units operate when required.
    5. Internal Bus: It is used to carry the byte (data or instructions) read from the memory to internal registers or to carry the internal data to external devices. So the acts as a connection between various units. The lower byte of the address bus and the data bus is internally multiplexed and is required to be demultiplexed when used in real application.
    6. Interrupt Control: this unit is used to accept the external interrupts such as TRAP, RST-7.5, RST-6.5, RST-5.5 and INTR and generates an acknowledgement signal INTA’ to acknowledge the receipt of the interrupt signal. Of these five interrupts TRAP, RST-7.5, RST-6.5, RST-5.5 are vectored interrupts and INTR is a non-vectored interrupts.
    7. Serial I/O control : this unit is responsible for receiving and sending the data serially to or from the processor. Two pins on the 8085 pin SID and SOD responsible for serial IN and OUT operation
    8. Address incrementer/Decrementer: This unit is responsible for incrementing or decrementing the content of PC so that it points to the next instruction. The address is then ready for demultiplexing and putting on the address bus.


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