LOGIC GATES
In this post we are going to learn about all the logic gates, their symbols, truth table and the logic equations. The different logic gates that will be covered are:
1. BUFFER 2. NOT 3. OR 4. AND
5. NAND 6. NOR 7. XOR 8. XNOR
Binary Values:
When only two possible states are to represented, we represent them by a ‘1’ or a ‘0’
What do ‘1’ or ‘0’ represent?
1: TRUE 0: FALSE
1: HIGH 0: LOW
1: YES 0: NO
Positive and negative Logic
Positive Logic 
Negative Logic 
Logic 1 represent à +5V  Logic 1 represent à à 0V or Ground 
Logic 0 represent à 0V or Ground  Logic 0 represent à +5V 
OR 

Logic 1 represent à High  Logic 1 represent à Low 
Logic 0 represent à Low  Logic 0 represent à High 
Truth Table:
A truth table is a tabular representation that describes the behaviour of the logic gate or circuit. It is a description of the relationship between the input and output. i.e. Given a circuit, it shows what the output will be upon application of the input
Logic Gates

Buffer:
A buffer produces the same output as its input. Buffer increases the signal strength at the output, so the signal can travel longer distance
Truth Table
A 
Y 
0 
0 
1 
1 
Waveform
In order to show output of a practical buffer we have to take the propagation delay time (tpd) into account. The output is shown shifted to the right by an amount equal to tpd.

INVERTER (NOT) Gate
An inverter negates or complements the input at its output.
For Example: If have a sample space of say decimal numbers as:
sample space = Σ(1,2,3,4,5,6)
Odd Numbers A = Σ(1, 3, 5)
Then
A’ = Σ( 2, 4, 6) all elements of sample space which are not part of A
But in Binary the sample space is
sample space S = Σ(0, 1)
If A = 0;
Then
A’ = 1
Or simply
0’ = 1
1’ = 0
Symbol
Truth Table
A 
Y 
0 
0 
1 
1 
Waveform
Cascading of Inverters
Inverters or NOT gates may be cascaded. The delay time at the output will then be additive of the propagation delay time of individual NOT gates.
Figure below shows the cascading of two inverters (NOT) gates
Waveform
The delay time at the output will then be additive of the propagation delay time of individual NOT gates.
Two inverters in cascade behaves like a buffer with delay = 2 tpd
In cascade the propagation of logic gates are added.
NOT Gate with Feedback
Waveform
Cascading of two Inverters with feedback
Waveform
We can see that for two inverters connected with feedback the output get stable after 2 tpd.
*** Therefore if even number of NOT gates are connected with feedback(in a loop) then the output remains stable at ‘0’ or ‘1’.
*** If odd number of NOT gates are connected in a loop the output generated will be a square wave
** In general the square wave so generated will have period of 2*N tpd, wher N is the number of NOT gates.
For 3 NOT gates in a loop; the period will be 2 * 3 tpd = 6tpd

AND Gate
It produces a high output when all inputs are high.It is also called as all high Pass gate.
Logic Symbol
Logic AND Operation: AND operation is denoted by a dot ‘.’.
Truth Table
A 
B 
Y=A.B 
0 
0 
0 
0 
1 
0 
1 
0 
0 
1 
1 
1 
Logic Equation:
Y = A.B
Commutative Law:
A.B = B.A
Associative Law
(A.B).C = A.(B.C)
AND Gate with Enable / Disable Input:
Enable or Disable input is used to control the behavior of the input at the output.
We can describe the behavior as:
If En = ‘1’ then Y = A, else Y = ‘0’
Floating Inputs: An AND gate whose one of the input line is unconnected is called to be in floating stae. Such a state can be fixed by connecting its open input to a ‘1’ or ‘0’ depending on what is required at the output.

OR Gate
It produces a high output when any or all of its inputs are high. It is also called as any High Pass gate.
Logic Symbol
Logic OR Operation:
OR operation is denoted by a plus ‘+’. Remember it is not an arithmetic addition
Truth Table
A 
B 
Y=A+B 
0 
0 
0 
0 
1 
1 
1 
0 
1 
1 
1 
1 
Logic Equation:
Y = A + B
Commutative Law:
A+B = B+A
Associative Law
(A+B)+C = A+(B+C)
OR Gate with Enable / Disable Input:
Enable or Disable input is used to control the behaviour of the input at the output.
We can describe the behaviour of an OR gate with Enable input as:
If En = ‘0’ then Y = A, else Y = ‘1’
Floating Inputs: An OR gate whose one of the input line is unconnected is called to be in floating state. Such a state can be fixed by connecting its open input to a Vcc or GND depending on what is required at the output.

NAND Gate
It is an AND followed by a NOT gate. It produces a LOW output when all its inputs are high, High otherwise.
Logic Symbol
Truth Table
A 
B 
Y=(A.B)’ 
0 
0 
1 
0 
1 
1 
1 
0 
1 
1 
1 
0 
Logic Equation:
Y = (A. B)’
Commutative Law:
(A. B)’ = (B.A)’
Associative Law : NAND gate does not follow associative Law
((A. B)’.C)’ ≠ (A.( B.C)’)’
NAND Gate with three inputs
Truth Table
A 
B 
C 
Y = (A.B.C)’ 
0 
0 
0 
1 
0 
0 
1 
1 
0 
1 
0 
1 
0 
1 
1 
1 
1 
0 
0 
1 
1 
0 
1 
1 
1 
1 
0 
1 
1 
1 
1 
0 
NAND Gate with Enable / Disable Input:
Enable or Disable input is used to control the behaviour of the input at the output.
We can describe the behaviour of an NAND gate with Enable input as:
If En = ‘1’ then Y = A’, else Y = ‘1’
Properties of NAND gate
(A.0)’ = 1
(A.1)’ = 0
(A.A)’ = A’
(A.A’)’ = 1

NOR Gate
It is an OR gate followed by a NOT gate. It produces a HIGH output when all its inputs are LOW.
NOR Logic Symbol
NOR Truth Table
A 
B 
Y=(A + B)’ 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
1 
0 
Logic Equation:
Y = (A +B)’
Commutative Law:
(A+ B)’ = (B+A)’
Associative Law :
NOR gate does not follow associative Law
((A + B)’ + C)’ ≠ (A + ( B + C)’)’
NOR Gate with three inputs
Truth Table
A 
B 
C 
Y = (A.B.C)’ 
0 
0 
0 
1 
0 
0 
1 
0 
0 
1 
0 
0 
0 
1 
1 
0 
1 
0 
0 
0 
1 
0 
1 
0 
1 
1 
0 
0 
1 
1 
1 
0 
Properties of NOR gate
(A + 0)’ = A’
(A + 1)’ = 1’ =0
(A + A) = A’
(A + A’)’ = 1’=0
NOR Gate with Enable / Disable Input:
Enable or Disable input is used to control the behaviour of the input at the output.
We can describe the behaviour of an NOR gate with Enable input as:
If En = ‘0’ then Y = A’, else Y = ‘0’

XOR (ExclusiveOR / EX–OR ) Gate
This gate is also called as the inequality detector. It produces a high output when odd number of inputs are high.
Symbol:
Truth Table
A 
B 
Y = A Ꚛ B 
0 
0 
0 
0 
1 
1 
1 
0 
1 
1 
1 
0 
Logic Equation
Y = A Ꚛ B
Logic Circuit
Commutative Law
A Ꚛ B = B Ꚛ A
Associative Law
A Ꚛ (B Ꚛ C) = (A Ꚛ B) Ꚛ C)
Truth Table of XOR gate with three inputs
A 
B 
C 
Y= A Ꚛ B Ꚛ C 
0 
0 
0 
0 
0 
0 
1 
1 
0 
1 
0 
1 
0 
1 
1 
0 
1 
0 
0 
1 
1 
0 
1 
0 
1 
1 
0 
0 
1 
1 
1 
1 
Properties of XOR gate
A Ꚛ 0 = A ( as buffer)
A Ꚛ 1 = A’ ( as inverter)
A Ꚛ A = 0
A Ꚛ A’ = 1
If A Ꚛ B = C then
A Ꚛ C = B and
B Ꚛ C = A This shows that XOR is cyclic
Exercise
What will be the output if we cascade even number of XOR gate as shown in figure
Answer:
After 2 XOR gates, output will be ‘A’; therefore, even number of cascaded XOR will produce the same output i.e. ‘A’

XNOR Gate:
A XNOR not gate is an XOR gate followed by an inverter. It is an equality detector gate. The output is high when even numbe of inputs are ‘0’ or Low.
Symbol
Truth Table
A 
B 
Y = A ʘ B 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
1 
1 
Logic Equation
Y = AB + A’.B’
OR
Y = A ʘ B
Logic Circuit
Commutative Law
A ʘ B = B ʘ A
Associative Law
A ʘ (B ʘ C) = A ʘ ( B ʘ C)
Properties of NOR gate
A ʘ 0 = A’ ( as inverter)
A ʘ 1 = A ( as buffer)
A ʘ A = 1 ( Always equal)
A ʘ A’ = 0 ( Always unequal)
Truth Table XNOR gate with three inputs
A 
B 
C 
X = A ʘ B 
Y= X ʘ C 
0 
0 
0 
1 
0 
0 
0 
1 
1 
1 
0 
1 
0 
0 
1 
0 
1 
1 
0 
0 
1 
0 
0 
0 
1 
1 
0 
1 
0 
0 
1 
1 
0 
1 
0 
1 
1 
1 
1 
1 
To summarize
XOR searches for odd number of 1’s
XNOR searches for even number of 0
For even number of inputs’s, XNOR = XOR’; this is verified in following truth table
A 
B 
XOR (A Ꚛ B ) 
XNOR (A ʘ B) 
0 
0 
0 
1 
0 
1 
1 
0 
1 
0 
1 
0 
1 
1 
0 
1 