Minimum vs Maximum mode operation of 8086


8080 and 8085 were used for single processor applications. In this sense 8086 is backward compatible with 8080 and 8085. that means when used in minimum mode, its function is similar to 8085, all control signals are generated on chip. But 8086 is an advanced processor and is built for complex applications involving multiprocessor  which generates all the control signals. In maximum mode the control signals are generated by use of 8288 bus controller and 8289 bus arbiter IC.

Differences between the Minimum and Maximum mode of operation:

Maximum mode Minimum Mode
When pin 33 MN / Mx is connected to GND. When pin 33  MN/Mx’ is connected to high.
In maximum mode 8086 generates QS1,QS0,S0′ ,S1′,S2′, LOCK(bar),RQ(bar)/GT1,RQ(bar)/GT0 control signals. and other signals are generated with the help of S0′, S1′ and S2′ 8086 generates INTA(bar), ALE, DEN(bar), DT/R(bar), M/IO(bar), HLDA,HOLD and WR(bar) control signals.
It is used for multi-processors system. Used in single-processor applications
Whereas in maximum mode interfacing, master/slave and multiplexing and several such control signals are required In minimum mode no interfacing or master/slave signals is required.
In maximum mode a bus controller is required to produce control signals. This bus controller produces MEMRDC, MEMWRC, IORDC, IOWRC, ALE, DEN, DT/R control signals. In minimum mode direct RD / WR signals can be used. No bus controller required. A simple demultiplexer would do the job. of producing the control signals. This demultiplexer produces MEMRD, MEMWR, IORD, IOWR control signals.

Maximum Mode of Operation

As seen, minimum mode system provides all control signals on 8086 chip itself thus reducing the the cost of the overall system but provide low functionality. On the other hand, for maximum mode a separate IC called 8288 Bus controller is used to provide control signals for memory and I/O operations.  This increases the system cost but at the same time increases the functionality. To keep the cost under control, resource sharing including sharing of bus mechanism is adopted. This would require an external bus controller 8288 for generation of many control signals.


Figure-1 below shows the pin function of the 8086 in maximum mode of operation.



8086 microprocessor works in maximum mode when its pin 33 MN/MX’ is connected to ground. This mode would now require additional circuitry such as 8288 bus controller for translating the control signals. 8288 bus controller converts the input control signals S0’, S1’ and S2’ from 8086 into the i/o and memory transfer signals needed for direct data transfers, and for controlling 8282 latches and 8286 transceivers.

Features of Maximum Mode:

When in Max Mode, it provides signals for implementing multiprocessor/ coprocessor system environment

Multiprocessor environment means that one processor exists in the systems and that each processor is executing its own program.

There are some system resources that are common to all processors. These resources are called global and local resources.

Both/All processors do not access the bus at the same time.


The function of pin 24 to 31 in maximum mode is given below:

PIN Number Symbol Function
31, 30 RQ/GT0,


REQUEST/GRANT:RQ/GT pins are used by other local bus masters to force the processor to release the local bus at the end of the processors current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and may be left unconnected.
29 LOCK’ LOCK output indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW.



Indicate the type of transfer to take place during the current bus cycle.

S2′ S1′ S0′ Characteristics
Interrupt Ack
Read i/o ports
Write i/o ports
Instruction fetch
Read Memory
Write memory
Inactive – passive
25 QS0 These pins reflect the status of the instruction queue and indicate the activity of the queue during previous clock cycle. The activity is given in table below:


0 0 No Operation during last clock cycle
0 1 1st byte of the instruction read from queue
1 0 Queue empty
1 1 Subsequent byte of instruction taken from queue



24 QS1


Maximum Mode Configuration of 8086

When MN/MX’ is connected to low logic, then 8086 is selected in maximum mode of operation. Now 8086 can operate in its full capacity for inter processor communication. The command and control signals are now generated by 8288. The connection with 8288 Bus controller, 8289 Bus arbiter and other components such as latches and transceivers is shown in figure. As seen the PIN S2’, S1’, s0’ is connected to 8288 bus controller. Depending on the status of the signal on  S2’, S1’, s0’ pins the command signals are generated by 8288. The control signals generated by 8288 are M/IO’, WR’, DEN, DT/R’, ALE etc and are not available on the 8086 microprocessor chip. Table below shows the commands in response to S2’, S1’, s0’ at the 8288 outputs

Figure-2 Max mode configuration


Figure in maximum mode configuration shows the connection to the 8289 bus arbiter. The inputs to the bus arbiter is LOCK’ and the status control signal S2’, S1’ and S0’.

The output signals generated by 8289 are:

  • Bus Busy ( BUSY’)
  • Common Bus Request (CBRQ’)
  • Bus Priority Output (BPRO)
  • Bus Priority In (BPRN)
  • Bus Priority Out(BREQ)
  • Bus Clock (BCLK)

All these above signals correspond to the bus exchange signals of the multibus and are used to lock other processors off the system bus during the execution of an instruction by the 8086. This way, processor can be assured of uninterrupted access to common system resources such as memory.

Queue Status Signals:

Pin number 24 and 25in maximum mode of 8086 indicate the queue status. QS1 and QS0 together form a two-bit queue status code as shown in the following table.

QS1 QS 0 Queue Status
0 0 No Operation. During the last clock cycle, nothing was taken from the queue.
0 1 First Byte. The byte taken from the queue was the first byte of the instruction.
1 0 Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction
1 1 Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction

when QS1,QS0 are 11, the status indicate that the instruction contains multi-bytes and are to be read from the queue. Depending upon the addressing mode the subsequent byte may contain the next byte of code or the data item.

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