Modes of IO Transfer

Modes of Transfer:

The data transfer between the CPU and the i/o device is through the memory. Data transfer between the CPU and I/O may be handled in a variety of modes. These are:

  1. Programmed I/O
  2. Interrupt I/O
  3. Direct Memory Access(DMA)

Programmed I/O Mode :

This mode uses the CPU as an intermediate path for the data transfer. Each data item is initiated by an instruction. Data transfer under this mode requires constant monitoring of the peripheral by checking the status flag which indicate whether the device is ready to receive or send the data. In this method the CPU stays in a program loop until the i/o unit is ready for data transfer. This method is quite slow.

Interrupt I/O

In this method instead of the CPU, the interface is used to keep track of when the peripheral is ready to receive or send information to the CPU. Meanwhile the CPU continues executing the main  When the i/o is ready for the data, the interface will communicate with CPU by sending an interrupt request for the data transfer. On receiving the interrupt request the CPU suspends the execution of main program and does the transfer activity requested by the interface. When the data transfer is completer, the CPU resumes  executions of the main program.

Direct Memory Access

In this mode, the interface transfers the data into and out of the memory unit through the memory bus. The CPU initiates the transfer by supplying the starting interface with the starting address and number of words needed to be transferred and then proceeds to execute other tasks. When the transfer is made, DMA requests memory cycle through the memory bus. When request is granted, the DAM transfers the data directly into the memory. The CPU merely delays its memory access operation to allow the direct memory i/o transfer.

Explain in details the three modes of transfer

Programmed IO example

In the programmed i/o mode all data transfer activity from the i/o to memory or vice versa take place through the CPU by executing a number of instructions. Figure shows the interface through which the i/o communicates with the CPU. Following steps of operation take place for i/o transfer.

Figure- Interface used between IO and CPU
  1. When the device is ready and data is available, it places the data on the i/o bus and enables the data valid line
  2. The interface accepts the byte into its data register and enables the data accepted line
  3. The interface sets the status flag to ‘1’ and disables the data valid line.
  4. The device disables the data accepted line and is now ready and can make another transfer.
  5. The CPU reads the status register and under program control constantly scans flag of the interface to check if the i/o has transferred a byte of data to its data register.
  6. If flag is set the CPU reads the data register else goes to step ‘v’.


Slow speed; Wastage of critical resource time of the CPU


Useful to systems with very slow speed that are dedicated to monitor a device.

Interrupt i/o

This mode overcomes the disadvantage of the programmed i/o. Instead of scanning the flag continuously as in programmed i/o, this mode allows the device to intimate the CPU through an interrupt signal when it is ready and has the data to transfer.  Figure below shows the functionality of this mode.

Figure – Flow of the interrupt system


    1. Device (interface) is ready the data in its data register it sets its flag.
    2. As the flag is set in the status register of the interface, it sends an interrupt signal to the processor.
    3. Processor save the return address given by PC onto the stack
    4. An ISR is called by loading the VAD to the PC to perform the transfer activity
    5. After the transfer control transfers to main program by POPing the stack to PC
    6. CPU continues with the normal execution of the main program.

Que. Explain the interrupt cycle and show the different microoperations performed during the interrupt cycle.


Interrupt cycle is explained with the help of the flow chart

Figure – Interrupt cycle

  1. When the interrupt flag R=0, the CPU goes through the instruction cycle to perform the normal operation.
  2. If the interrupt enable flag “IEN” is enabled, then CPU checks if the input flag or the output flag is set or not.
  3. If either the FGI or FGO is set, interrupt flag R is set to ‘1’ and the CPU then goes through the interrupr cycle.
  4. The CPU stores the return address given by PC onto the stack in location M[SP]
  5. Vector address(VAD ) of ISR loaded in PC and starts executing the instruction for transfer operation.
  6. CPU also clears the IEN and R flag so that no more interrupt can occur until the interrupt request has been serviced.

List of micro-operations performed by the CPU during the interrupt cycle.

SP <– SP-1;          Determine the stack pointer

M[SP] <– PC;      Push PC onto the stack

INTACK <– 1;      Enable interrupt acknowledgement

PC <– VAD;         Transfer vector address to PC

IEN <– 0;              Disable the further interrupt

Go to fetch the next instruction

 Direct memory Access(DMA)

This mode removes the processor from the external bus and lets the peripheral device manage the transfer directly to memory. This way it improves the speed of transfer and make the system more efficient. During DMA transfer, the CPU is idle and no longer has the control of system bus. The control of the bus is taken over by the DMA controller.

Figure – Direct Memory Access


    1. The peripheral device sends DMA request.
    2. DMA sends the Bus request(BR) to the CPU to relinquish the buses
    3. CPU responds with the Bus grant (BG) informing DMA that its buses are now disabled.
    4. DMA puts the current value of its address register on to the address bus and initiates a RD or WR signal.
    5. DMA then sends the acknowledgement to the peripheral device
    6. Peripheral then puts a byte of data on the data bus or receives a byte from the data bus. The peripheral now communicates with the memory for direct data transfer. The CPU is momentarily idle during this time.
    7. For each byte transfer the DMA increments the address register and decrements the count register.
    8. If the count register is not zero, peripheral continues with the next transfer until the entire block of data is transferred.
    9. If the count register reaches zero, DMA stops further transfer.
    10. The bus request line is deactivated.
    11. The CPU disables the BG line and takes control of the buses back for the normal operation.

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