Introduction to Multiplexer:

A multiplexer, also called as a data selector, is a combinational circuit used to select information from one of the many input sources and directs it to a single output line.

A multiplexer has several data input lines but only one output. Control or selection lines are used for selecting one of the input lines.

Multiplexers come in sizes 2^N x1 (like 2×1, 4×1, 8×1,16×1 etc). In general, a multiplexer has 2^N input lines, N control lines and 1 output line. Figure-1 shows the General block diagram of a multiplexer.

2×1 Multiplexer

A 2×1 multiplexer will have two inputs, one selection or control line and one output. The output equation of a 2×1 multiplexer is :

Y= I₁.S + I₀.S’

Multiplexer may also have an active high or low enable line, in which case the output equation of a 2×1 multiplexer will be:

Y=EN.( I₁.S + I₀.S’)              for active High enable (EN) line or

Y= EN’ (I₁.S + I₀.S’)              for active low enable (EN’) line

4 to 1 Multiplexer:

A 4×1 multiplexer has 4 input lines say I₃, I₂, I₁, I₀ and 2-control or select lines S₁, S₀. Table-1 shows the relationship between inputs, select line and the output for 4×1 multiplexer.

The output Logic equation is :

 

 

 

 

 

 

 

 

The logic expression of 4×1 multiplexer is given in figure-2 and replicated below:

Y = S₁S₀I₃ + S₁S₀‘.I₂ +  S₁‘S_0.I₁ + S₁‘.S₀‘.I₀

Operation of 4×1 Multiplexer:

1. When S₁S₀ = 00, the upper AND gate is enabled, so data input I₀ is passed to the the output.
2. When S₁S₀ =01, the 2nd AND gate from top is enabled, thus I₁ is passed to the output.
3. When S₁S₀=10, the 3rd AND gate get enabled, and hence I₂ is passed to output.
4. Finally, when S₁S₀ = 11, the input I₃ is passed to the output.

Extending the Size of Multiplexer:

Large multiplexer can be implemented using smaller size multiplexers.

 

For example, consider an 8×1 MUX can be implemented using two 4×1 MUXs and one 2×1 MUX as shown in Figure-3

S₁S₀ are used to select one of lines from either I₁, I₂, I₃, I₄ or from I₅, I₆, I₇, I₈.

Now we have two outputs one each from  top and the bottom multiplexers which act as input to a 2 x 1 multiplexer.

Select line S₂ is used to select one of the input of 2×1 multiplexer to be connected to the output logic.

Implementation using 2×1 multiplexers:

 A 4×1 Mux requires three 2×1 multiplexers, a 8×1 requires seven 2×1 multiplexers, a 16×1 require fifteen 2×1 multiplexers.

In general, 2ⁿ x 1 MUX is implemented using (2n- 1) 2 x 1 MUX.

To implement using different size multiplexers:

The following formula is used to implement B x 1 MUX using A x 1 MUX ,

B / A    =          K1,
K1/ A =          K2,
K2/ A =          K3

………………

K_N-1 / A            =          K_N = 1 (till we obtain 1 count of MUX).

And then add all the numbers of MUXes = K1 + K2 + K3 + …. + K_N.

For example​ : To implement 64 : 1 MUX using 4 : 1 MUX
Using the above formula:

64 / 4 =          16
16 / 4 =          4
4 / 4     =          1

Hence, total number of 4 : 1 MUX are required are = 16 + 4 + 1 = 21.

Implementing logic function with Multiplexer:

So, multiplexer is a readymade circuit for implementing the SOP equation in the form of AND-OR logic. AND logic inside a multiplexer implements the minterms or the product terms whereas the OR logic performs the sum of these minterm.

As the minterms are formed for high ‘1’ outputs, for implementing any SOP function we need only to connect inputs lines of the multiplexer corresponding to the minterms of the SOP  equation  to Vcc and the rest inputs pins of the multiplexer to the ground.

Example-1: Implement the two variable function F(AB) = ∑m(0,1,3) using the Multiplexer.

Sol: F(AB) = ∑m(0,1,3)

Figure-3: Implementation of logic function with multiplexer

As discussed above, the control input S1S0 decides which combination is selected for output.

Thus we can connect I0, I1, I3 to Vcc and I2 to the Ground.

 

 

Example-2:

The output logic equation Y of the 4×1 multiplexer shown in figure is:

Solution:

Y     =          A’B’C + A’BC +AB’C’ + ABC’

=          A’C(B’+B)  + AC’(B’+B)

=          A’C        +       AC’

=          A  ⊕  C

Example-3:

What logic equation is implemented by the network of Mux shown in figure:

Solution:

F2       =          f1’.1 + f1.A’

F1        =          C’.0 + C.B

Therefore

F2       =          (BC)’ + A’BC

=          A’ + (BC)’

=          A’ + B’ + C’                ((BC)’ = B’+C’)

Implementing with Demultiplexures

A demultiplexer is a combinational circuit that is used to transfer the data from a single input line to one of the many output lines. The demultiplexer has one input line, N control lines, and 2N output lines.

Demultiplexure Symbol

 

 

 

 

 

Truth Table of Demultiplexure

Input	S2	S1	O1	O2	O3	O4
I1	0	0	I1	0	0	0
I1	0	1	0	I1	0	0
I1	1	0	0	0	I1	0
I1	1	1	0	0	0	I1

The outputs O1=I1S2’S1′;      O2= I2S2’S1;              O3= I3S2S1′;              O4= I4S2S1

Following figure shows the implementation of the logical expression of a demultiplexure.

 

 

 

Exercises:
1.         Implement a 16 x 1 multiplexer using 8 x 1 Multiplexer
2.         Implement the following F(A,B,C,D) = SOP(2,4,5,7,9,11,13,14,15) using a 8 x 1 Multiplexer

QUIZ:

 

3. The logic function realized by the following multiplexer circuit is:

(a). A ⊕ B

(b). A ⊕ C

(c). A ⊕ B ⊕ C

(d). None of the above

4. Output of the 4×1 multiplexer shown is.

• A.B.C
• A xor B xor C
• A xnor B xnor C
• A + B + C

5. If a 4×1 Mux shown below realizes a three variable function f(x,y,z)=xy + xz’, then which of the following is correct

• I0 = X, I1 = 0,             I2 = X,            I3 = X
• I0 = 0, I1 = 1,              I2 = Y1,           I3 = X
• I0 = X, I1 = 1,              I2 = 0,                        I3 = X
• I0 = X, I1 = 0,             I2 = X,            I3 = Z

 

6. The circuit shown is figure is same as:

• Two input NAND gate with a and c input
• Two input NOR gate with a and c input
• Two input XOR gate with a and b input
• Two input XNOR gate with b and c input

7. In the circuit find ‘X’

• AB’C’ + A’BC’ + A’B’C + ABC
• A’BC + AB’C +ABC’ + A’B’C’
• AB + BC + CA
• A’B’ + B’C’ + A’C’

8. Find the function implemented:

• PQ + PS + Q’R’S’
• PQ’ + PQR’ + P’Q’S’
• PQ’R’ + P’QR + PQRS + Q’R’S’
• PQR’ + PQRS’ + PQ’R’S + Q’R’S’

9. For the multiplexer to function as a full adder what should be the input provided to the I0, I1, I2, I3 if A and B are the select lines

 

• I0 = I1 = Cin; I2 = I3 = Cin’
• I0 = I1 = Cin’; I2 = I3 = Cin
• I0 = I3 = Cin; I1 = I2 = Cin’
• I0 = I3 = Cin’; I1 = I2 = Cin

 

10. A function has been implemebted using a MUX shown, implement the same function with a and c as select lines.

(a)

 

 

(b).

(c)

(d)