Operator Overloading in VHDL

At times, the coder need to use the same operator for processing objects of different type. For example, VHDL has a predefined operator ‘+’  to add two integers, what is we add two characters, add two real values, add two strings, add two vectors and so on. VHDL and any other language do not have seperate operator for those purpose and thus would demand for a separate operator. As the number of operators increase it’ll be hard to remember them.


Overloading allows the coder to write separate subprograms for the same object (operator) to perform on values of different types. An operator is overloaded by defining a functionality other than its pre-defined meaning. This is done by defining a function and the name of such function is same as the operator symbol except that the operator is double quoted as shown below:

Function “+” (formal parameters) return <return type> is



End ;

The follwoing VHDL code first creates a package “my_Math” which has two function prototypes “con_vec_to_int” and “+” and their functions. The function “+”  is created to define addional functionality to “+” i.e. how to add vector quantities. As a new definition or functionality is defined for “+”, the “+” is said to be overloaded and now has two meanings attached to it one is the predefined operation and a new operation on vector. See the example below:

PACKAGE inside MY_LIB library

library IEEE;

use IEEE.STD_LOGIC_1164.all;

package my_Math is

function con_vec_to_int (s: bit_vector) return integer;

function “+”(l,r : bit_vector) return integer;

end my_Math;

package body my_Math is

function con_vec_to_int (s: bit_vector) return integer is

variable prod : integer := 1;

variable result : integer:=0;


FOR i in s’range LOOP

if (s(i) =’1′) then

result := result + prod;

end if;

prod:= 2 * prod;

end loop;

return result;


function “+” ( l, r : bit_vector) return integer is


return (con_vec_to_int(l) + con_vec_to_int(r));


end my_Math;

–VHDL code for arithmetic addition

library IEEE;


library my_lib;

use my_lib.my_math.all;

entity adder is

port ( a : in BIT_VECTOR(3 downto 0);

b : in BIT_VECTOR(3 downto 0);

c : in integer;

d : out integer);

end adder;

architecture Behavioral of adder is

signal temp: integer;


temp <= con_vec_to_int(a) + con_vec_to_int(b);

d <= c + temp;

end Behavioral;


  • What do you understand by overloading? Explain overloading in VHDL.

  • What do you understand by delays in VHDL, what are its types.

  • Write short notes on inertial delay and transport delay and delta delays with example.

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