Sequential Style Modeling

Sequential style of modeling is also called the behavioral style. This style of coding make use of the process statement(s). Once an entity is declared, the a process is defined inside the architecture. Sequential code inside the process allows statements like IF, CASE, LOOP and WAIT and the desired operators inside the code.The general structure of a behavioural style modelling in VHDL is given below:

LIBRARY <library_name>;

USE library_name.<package_name>.all;

ENTITY <entity_name> IS


Signal_name(s) : mode type ;

Signal_name : mode type


END [ENTITY] [entity_name] ;

ARCHITECTURE behavioural OF<entity_name> IS

–declaration of signal, constant, type;


–concurrent statement

–[process_label :] PROCESS [(sensitivity list)]

–variable, constant declarations;



End PROCESS[process_label ];

END [Architecture] [behavioural];

As seen in the above prototype VHDL code, a sequantial code need a process statement. To make the code  sequential,te statements have to be written inside a subprogram (like process, function or procedure. The use of the sequential statements for a VHDL code makes it look like a code of a traditional programming language like C.  The sequential statements are discussed below:

Concurrent vs Sequential statement example

Concurrent statement example

signal x : std_logic <= ‘0’;

signal assignment statement as above in the architecture  is also in fact a process and is always active (sensitive) to signals on the right hand side, having a single target

Sequential statement example

variable x : std_logic;

if x = ‘0’ then


end if

Difference between process and signal assignment statement

Signal assignment statement

Process statement

It has only one target which is on the left of <= operator

process may have multiple targets inside the statement part of process,

All signal assignment statements are executed concurrently

All the statement inside this process statement execute sequentially

Process statement

Process in itself is a concurrent statement.  It describes the functionality of an entity in sequential form. Any assignments made inside the process are not visible outside the process. When the process statement get invoked during execution all the statements inside the process get executed in the order they are written till the last statement “end process” is encountered when the process get. The format of process statement is shown below:

[Label ] : process    [(sensititivity list) ] [ is]

— declaration of process items like variables etc


–Variable assignment statement(s)

–Signal assignment statement(s)

–Wait statement

–If statement

–Case statement

–Loop statement

–Null statement

–Next statement

–Assertion statement

–Report statement

–Procedure call statement

–Return statement

End process [process label];

As seen in above prototype, a process statement may contain sequantial and the concurrent statement both. If, If-else, case, next, procedure call and return are the some of the sequential statements.  suspended.

Sensitivity List

The sensitivity list is all the input signals which are used inside the process. It is defined between the process and is keywords and enclosed within []. The process becomes active whenever there  is any change in value of the signal in the sensitivity list. It should be noted that the end of process does not stop the simulation rather it waits for another event to occur on the signal in the sensitivity list.

label : process [ clock, X, Y]


end process [label]

here clock, X and Y are the sensitivity list. The process named label will become active whenever ther is a change in clock, input X or input Y.


  1. Give the general structure of behavioral style of modeling showing the different statements used in the architecture with the help of an example.
  2. What is a process statement? Write the syntax of process statement
  3. Write short notes on variable assignment Statement.
  4. Write short notes on signal assignment Statement.
  5. Explain Wait statement with relevant example.

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