Synthesis of Multiplexer

Write VHDL programs for the following circuits, check the wave forms and the hardware generated

  1. multiplexer   De-Multiplexer

Objective:

  1. To learn the VHDL coding for Multiplexer
  2. To understand the behavior of Multiplexer
  3. To Synthesize multi-bit MUxes
  4. To Synthesize larger MUXs using smaller MUXs
  5. To simulate Multiplexer

Theory:

A multiplexer is a combinational circuit which has 2N:1 input output ports with N and control ports. The control port is used to select one of the 2N input and connect it to the output. A multiplexer is also called a switcher as it switches one of several input lines through to a single common output line.

The block diagram representation is given below:

Figure: Symbol of MUX

The output equation of a 2×1 multiplexer is given below:

Y = I0 . S’ + I1 . S

The VHDL code for synthesizing the 2×1 multiplexer is given below in all the three style of modelling.

Dataflow Modeling

VHDL CODING

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

 

entity MUX2x1 is

Port (

I : in  STD_LOGIC_VECTOR (1 downto 0);

s : in  STD_LOGIC;

 y : out  STD_LOGIC

);

end MUX2x1;

architecture Behavioral of MUX2x1 is

begin

Y <= (I(0) and (not s)) or (I(1) and s);

end Behavioral;

 

 

Behavioural Modeling

Behavioural Modelling of 2×1 multiplexer in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux2x1_behave is

Port (

i : in  STD_LOGIC_VECTOR (1 downto 0);

s : in  STD_LOGIC;

y : out  STD_LOGIC

);

end mux2x1_behave;

architecture Behavioral of mux2x1_behave is

begin

mux2x1: process (i,s)

begin

if ( s=’0′) then

Y <= i(0);

elsif( s=’1′) then

Y <= i(1);

else

 y <= ‘Z’;

end if;

end process;

end Behavioral;

 

Structural Modeling

Designing a 4×1 multiplexer using 2×1 multiplexers in structural modelling

A 4×1 multiplexer can be implemented in structural modelling using VHDL by using three 2×1 multiplexers. The block diagram and the VHDL code is shown below.

Figure: Structural Style of MUX

 

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity MUX4x1 is

Port (

i : in  STD_LOGIC_VECTOR (3 downto 0);

s : in  STD_LOGIC_VECTOR (1 downto 0);

y : out  STD_LOGIC

);

end MUX4x1;

architecture struct of MUX4x1 is

signal w1,w2: std_logic;

begin

X1: entity work.mux2x1 port map (

I(0)=>I(0), I(1)=>I(1),s=>s(0), y=>w1

);

X2: entity work.mux2x1 port map (

I(0)=>I(2), I(1)=>I(3),s=>s(0), y=>w2

);

X3: entity work.mux2x1 port map (

I(0)=> w1, I(1)=>w2,s=>s(1), y=> Y

);

end struct;

 

Test Bench for MUX 4×1:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY mux_4x1_tb IS

END mux_4x1_tb;

 

ARCHITECTURE behavior OF mux_4x1_tb IS

— Component Declaration for the Unit Under Test (UUT)

COMPONENT MUX4x1

PORT(

i : IN  std_logic_vector(3 downto 0);

s : IN  std_logic_vector(1 downto 0);

y : OUT  std_logic

        );

END COMPONENT;

–Inputs

signal i : std_logic_vector(3 downto 0) := (others => ‘0’);

signal s : std_logic_vector(1 downto 0) := (others => ‘0’);

–Outputs

signal y : std_logic;

BEGIN

— Instantiate the Unit Under Test (UUT)

uut: MUX4x1 PORT MAP (

i =>i,

s => s,

y => y

        );

— Stimulus process

stim_proc: process

begin

— hold reset state for 100 ns.

wait for 1000 ns;

— insert stimulus here

i<= “0001”;

s<= “00”;

wait for 1000 ns;

      i<= “0001”;

s<= “00”;

wait for 1000 ns;

       i<= “0010”;

s<= “01”;

wait for 1000 ns;

      i<= “0100”;

s<= “10”;

wait for 1000 ns;

      i<= “1000”;

s<= “11”;

wait for 100 ns;

wait;

end process;

END;

Simulation

Figure : Simulation of MUX

Special MUX

Special Type of Mux:

Now we move a step further in defining a multi-bit output multiplexer. Here we illustrate a mux2x1_4bit that accepts two four bit input number on its two input ports A and B. The “sel” input is used to select one of the two four bit input and passes it on the four bit output shared bus. The general bloc for a MUX2x1_4bit is shown below followed by the VHDL concurrent style of modelling.

VHDL CODE:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY mux2_1_Nbit_wide IS

Generic ( N: integer :=4);

PORT(

in_a : IN STD_LOGIC_VECTOR(N DOWNTO 0); –input a

in_b : IN STD_LOGIC_VECTOR(N DOWNTO 0); –input b

sel : IN STD_LOGIC; –select input

output : OUT STD_LOGIC_VECTOR(N DOWNTO 0) –data output

              );

END mux2_1_Nbit_wide;

ARCHITECTURE dataflow OF mux2_1_Nbit_wide IS

BEGIN

WITH sel SELECT

output<=         in_a WHEN ‘0’,

in_b WHEN ‘1’,

(OTHERS => ‘X’) WHEN OTHERS;

END dataflow;

Note:  OTHERS used to match cases where sel is not ‘1’ or ‘0’ in the (OTHERS => ‘X’) WHEN OTHERS; OTHERS is also used to provide a shorthand method of saying, “make all the bits of the target signal ‘X”

 

Updated: August 11, 2019 — 10:18 am

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