Memory Organization Computer Organization and Architecture by Ravinder Nath Rajotiya - January 4, 20230 Memory Organization Every computer system has following types of memory devices. The different types of memory can be explained as the memory hierarchy. Memory Hierarchy: The total capacity of the memory in a system can be visualized as a hierarchy of memory devices. It includes all memory devices employed in a computer from large size but very slow-speed to small size but very-high speed devices. The memory hierarchy can be represented as shown in figure below. IOP is used to communication between main memory and the auxiliary memory. Cache is used to communicate between CPU and the main memory. Internal or the primary memory: The internal memory consists of random access memory (RAM), read only memory (ROM) and some high-speed memory such as cache memory.
8086 memory Organization 8086 Microprocessor by Ravinder Nath Rajotiya - March 30, 2022March 30, 20220 8086 supports 1M byte of memory. To address 1MB, we need 20 address lines and the 20 bit address ranges from 00000000000000000000 –to- 11111111111111111111 i.e. 00000h to FFFFFh. The memory is constructed using RAM and ROM /EEPROM chips. 1MB memory can be contagiously organized as memory or can be organized in banks of odd and even address memory so as to access 8 or 16 bit of data. The 8-bit data thus we can either access bytes from even address on data lines D0-D7 and data from odd address on the data bus D8-D15. Approached to Memory organization: i. As one contiguous block: Memory can be organized as one contiguous block of memory as in 8085 based systems. In this case 8-bit data
8085 Memory Organization 8085 Microprocessor by Ravinder Nath Rajotiya - September 24, 2021September 24, 20210 8085 Memory Organization 8085 has 16 address lines, so it can address up to 64KB of memory. This 64KB may be one single IC or can be made using smaller memory IC. The operations on the memory IC can be a memory read or memory write. We can connect the RD’ or WR’ lines from the microprocessor to the coprresponding RD’ and WR’ pins of the memory IC. Thses signals can also be generated by an external logic Figure above shows the necessary signals in addition to the pins on a typical 64 Byte memory module. These signals are: 6 address lines ( because 2^6 = 64) 8 address lines to carry 8-bit of data Control lines as RD’, WR’ and CS’ (chip select) The memory