Introduction In this article we will discuss the design of the arithmetic adder and subtracter circuits. These circuits will take input bits and produce two outputs sum and carry or difference and borrow. Half adder A half adder is a logic circuit that adds two bits at a time. These two bits may be the bits of two binary numbers or a bit of one number and a carry from previous stage. This circuit take two inputs and produces two outputs a Sum and a Carry. Truth table of a half adder The Sum output has two minterms and the carry output has one minterm. So the output equation in SOP form is Boolean equation are: Sum = A’B + AB’ Carry = AB The above equations do

# Tag: not

# Operators in VHDL

OPERATORS VHDL has a wide set of operators. These are specific to the data types, all operators do not operate on every data types. They are further divided into groups of the same precedence level (priority).Table below shows all operators as per their precedance low to high, row-1 has the lowest priority whereas operators of row-7 has the highest priority. Within each row the priority is from left to right with the leftmost having highest priority. Class Operator Precedence Low high Same Operator Precedence (Applied Left –to-Right) 1. Logical operators and or nand nor xor xnor 2. Relational operators = /= < <= > >= 3. Shift operators sll srl sla sra rol ror 4.Addition operators + = & 5. Unary operators + - 6. Multiplying op. * / mod rem 7. Miscellaneous op. ** abs not The order of precedence is the highest for the operators of class 7, followed by class 6 with the lowest precedence for class 1. Unless parentheses are

# Logical and Shift Micro-operations

Logical Shift micro-operations: The logical operations that are performed on the contents of the processor register are called as the logical micro-operations. These micro-operations are AND, OR, INVERT, XOR etc. are performed on individual bits of the registers As an example, logical exclusive-OR micro-operations can be written as: X: R3 <-- R1 ⊕ R2 This RTL syntax describes that R3 is update with the result of the exclusive-OR operation on the contents of R1 and R2 when the control signal X goes high. We are aware that a ‘+’ means an arithmetic addition as well as a logical OR operation. To avoid the confusion in the use of the symbols the OR operation will be indicated by ‘V’ and the arithmetic operation by ‘+’ symbol.

# Logical and Shift and Rotate Instructions 8086

LOGICAL Group of Instructions. Bit manipulation instruction Bit Manipulation instructions : The instruction in this category operate on bits. The instruction can set, reset or even can test a particular bit. These instructions include : Logical instructions: NOT, AND, OR, XOR and Test. FORMAT Example Comments Flags Affected NOT Source (R/M) MOV BL, 35h NOT BL BL=00110101 BL= 11001010 AND (R/M), Imm./ R/M MOV AL, 35h AND AL, 0Fh AL=00110101 AL=AL.0Fh= 00000101 CF=OF=0, AF=? PF, SF, ZF updated OR (R/M), Imm./ R/M MOV BL, 22h MOV CL, FFh OR BL, CL BL=00010110 CL=11111111 BL=BL+CL=11111111 CF=OF=0, AF=? PF, SF, ZF updated XOR (R/M), Imm./ R/M MOV AL, 55h XOR AL, FAh AL=01010101 AL xor FAh=10100111 CF=OF=0, AF=? PF, SF, ZF updated TEST R?M, Imme/R/M MOV AL, 51h TEST AL, 80h AL=01010001 Test AL,80 test if the MSB is 0 or not; if msb is zer0 Z flag will be set. CF=OF=0, AF=? PF, SF, ZF updated 2. Shift and Rotate operation These instructions are

# Axioms and Laws of Boolean Algebra

Boolean Algebra Axioms and Laws of Boolean Algebra Boolean algebra devised in 1864 by George Boole, is a system of mathematical logic. It is an algebraic system consisting of a set of element (0,1) associated with a Boolean variable and two binary operators AND and OR and a uniry operator NOT. In mathematics, an identity is a statement true for all possible values of its variable or variables. Axioms AND Operation 0.0=0 0.1=0 1.0=0 1.1=1 2. OR Operation 0+0=0 0+1=1 1+0=1 1+1=1 3. NOT Operation 0’ = 1 1’ = 0 Identities: In mathematics, an identity is a statement true for all possible values of its variable or variables. Identity Boolean Relation Symbol Additive Identity A + 0 = A A + 1 = 1 A + A = A A + A’ = 1 Multiplicative Identity A . 0 = 0 A . 1 =