VHDL Modeling Styles

VHDL Modeling Styles

  1. Concurrent or Dataflow Modelling:

The Dataflow description is built with concurrent signal assignment statements. Each of the statements can be activated when any of its input signals changes its value. This is shown with the help of a 2-to-4 decoder. The output of the decoder is used to illuminate one of the four LEDs. The entity is given in the following code in VHDL

Entity Decoder_bcd is

Port (

A, B : in std_logic;

O : out std_logic_vector( 3 downto 0)


End entity Decoder_bcd;

architecture Dataflow of Decoder_bcd is


O(3) <= A and B;

O(2) <= A and (not B);

O(1) <= (not A) and B;

O(0) <= (not A) and (not B);

end Dataflow;

All the four statements here are executed concurrently and each of them is activated individually when any of its input signals changes its value.

2. Behaviour (Functional) Model:

The architecture body describes only the expected functionality (behavior) of the circuit, without any direct indication as to the hardware implementation. The architecture of the behavioral model may consist of one or more process statements, each of which contains sequential statements. It should be remembered that process statement themselves are concurrent statements, but all the statement inside a process statement are sequential in nature. The code below shows the behavioral style of model in VHDL

entity Decoder_bcd is

Port ( in_X : in std_logic_vector(1 downto 0);

O : out std_logic_vector( 3 downto 0);

End entity Decoder_bcd;

architecture procedural of Decoder_bcd is

signal S: std_logic_vector (3 downto 0);


P1: process (in_X, S)


case in_X is

when “00” => S <= “0001” after 5 ns;

          when “01” => S <= “0010” after 5 ns;

          when “10” => S <= “0100” after 5 ns;

          when “11” => S <= “1000” after 5 ns;

end case

O <= S;

end process;

end procedural;

The clause “after 5 ns” here allows to introduce time delay of the circuit. The assignment of a new value to the led signal will be done only after 5 nanoseconds of the simulated time.

3. Structural Modelling:

The structure modelling makes use of components instantiations which are either part of library or otherwise and the generate statements. It allows creating hierarchical projects, from simple gates to very complex components, describing entire subsystems. The components are connected together at the ports with the help of wires (signals) which are declared in the architecture of the structure model in VHDL. Components which are not part of libraries may also be declared in declarative part of the architecture. The code below explains the concept of structure modelling for a BCD decoder.

Figure 4.1: Decoder design using AND and NOT

architecture Structure_Modeling of BCD_Decoder is

signal S: Bit_Vector(0 to 1);

component AND_Gate
  port(A, B:in Bit; D:out Bit);

end component;
component Inverter
port(A: in Bit; B:out Bit);

end component;


X1:Inverter port map (A=>in_X(0), B=>S(0));
X2:Inverter port map (A=>in_X(1), B=>S(1));
Y1:AND_Gate port map (A=> in_X (0), B=> in_X (1), D=>O(3));
Y2:AND_Gate port map (A=> in_X (0), B=>S(1), D=>O(2));
Y3:AND_Gate port map (A=>S(0), B=> in_X (1), D=>O(1));
A4:AND_Gate port map (A=>S(0), B=>S(1), D=>O(0));

end Structure_Modeling ;

The components Inverter are instantiated under X1, X2 names and AND_Gate are instantiated under the names Y1, Y2, Y3 and Y4. The connections among the components are realized by the use of signals S(0), S(1) declared in the architecture’s declarative part.

4. Mixed Style Modelling:

This style of architecture comprises of both the behavior and structure of the circuit at the same time. Such architecture description using the sequential and structural modelling is called mixed style of modelling. The complete code of such a modelling is shown below:

Entity  decoder is

Port (

in_X:in bit_vector(1 downto 0);

O: out bit_vector(3 downto 0)


End entity Decoder;

architecture Mixed of Decoder_bcd is

signal S: Bit_Vector(0 to 2);

component Inverter
port(A: in Bit; B: out Bit);

end component;


Inv1: Inverter port map (A=>in_X(0), B=>S(0));

Inv2: Inverter port map (A=>in_X(1), B=>S(1));

P: process (S, bcd)


      O(0) <= S(0) and S(1) after 5 ns;

      O(1) <= S(0) and bcd(1) after 5 ns;

      O(2) <= bcd(0) and S(1) after 5 ns;

      O(3) <= bcd(0) and bcd(1) after 5 ns;

end process;

end Mixed;

 Above, two Inverter component instantiation statements define the circuit responsible for determining the value of the signal S. This signal is read by behavioral part i.e. the process statement P. In this process, the values computed by the “and” operation are assigned to the led output port.


  • Briefly Describe the Data Flow style of Modeling

  • Briefly Describe the Behavioral style of Modeling

  • Briefly Describe the structural style of Modeling

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