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Design of ALU

Design of ALU

ALU forms one of the important block of a digital computer. It is a multi-operation, combinational circuit. Number of operations supported depend on the complexity of its design. It takes two numbers of n-bit wide as input, performs an operation depending on the function select inputs and produces the output Fn, It also has carry-in input to provide additional functionality and carry-out line which can be part of the result or can act as input to the next stage when the functionality is extended to accommodate numbers with more number of bits. If an ALU has k function select lines, then it will have 2k operations. Figure-1 shows the block diagram of an ALU.

Figure-1: Block diagram of an ALU

Modular design technique can be used to divide the ALU into two separate units called as arithmetic unit and the second as the logical unit.

Design of an arithmetic unit

1’s and 2’s complement arithmetic allows both the addition and the subtraction to be performed only adding the two numbers. Positive numbers can be added just as binary addition, whereas a number can be subtracted by adding complement of -ve number with the other number. Two -ve numbers can be added by taking complement of both numbers and adding them together.

2’s  complement Adder subtractor

The two’s complement addition subtraction can be performed using the following general equation :

  • addition F = A + B + Ci; where Ci = 0 for addition
  • subtraction F = A + B’ + Ci; where Ci = 1 for subtraction

We observe that :

  • For addition Ci = 0 and B in uncomplemented form
  • For subtraction Ci = 1 and B complemented

Ci or the carry-in plays an important role of mode control for addition and subtraction. When Ci=0, addition of A and B is performed, when Ci=1; B is complemented to perform subtraction. This is elaborated in the truth table

Figure-2: Implementing NOT using XOR function

So, inversion can be performed with XOR gate when Ci = ‘1’. This can be used in one of the input of a FA to either pass B as it is or B’. Ci acting as the mode control.

2’s complement 4-bit Adder Subtractor:

Using the above concept of using XOR with Ci acting as a mode control bit, we can easily construct a 4-bit adder subtractor using 2’s complement  arithmetic. This is shown in figure-3

Figure-3 : A 4-bit 2’s complement adder subtractor circuit

Addition: F = A + B + Ci

To add two 4-bit numbers A and B, set M=0, this will make Ci=0 and the B will be passed through the XOR. FA will then add it as S = A + B + 0

Subtraction:  F = A + B’ + 1

To subtract two 4-bit numbers using 2’s complement arithmetic, set M = 1, this will make Ci=1 and the B will be complemented and passed through the XOR. FA will then add it as S = A + B’  + 1

A general Arithmetic Unit

This way we make use of the full adder(FA) as the basic component. Some of the useful arithmetic operations are listed below:

  1. Addition:                                F = A+B
  2. Add with carry :                     F = A+B+1
  3. 1’s complement A-B;             F= A+B’
  4. 2’s complement subtraction  F = A+B’+1
  5. Transfer : F = A;    or             F = A+0
  6. Increment by ‘1’,                    F = A+1
  7. Decrement : F = A-1 ie          F = A+ all 1’s       or F = A + 2^N – 1
  8. Transfer : F= A  e.                  F = A+ all1’s +1   or F= A + 2^N + 1

Now it is clearly noticed that to perform the above operations we need operand A and the 2nd operand as ‘0’, B, B’ or 1.  We can directly input the variable A to the FA, and the 2nd input is to be generated wither using logic gates or using a multiplexer.

How to generate the 2nd input for the Full Adder to perform one of the above operation. This is shown in figure-4

Figure-4: Generation of 2nd input (‘0′, B, B’, ‘1’)  for the FA
  • When S1S0=00, Y output is ‘0’ irrespective of the value of B
  • When S1S0 = 01, the upper AND gate is active to produce the output Y = B
  • When S1S0 = 10, the Lower AND gate is active to produce the output Y = B’
  • When S1S0 = 11, Both the AND gate are active to produce the output Y = B+ B’ =1

This is what is need for the 2nd input of the arithmetic unit

Logic diagram of the arithmetic circuit

We now use the above circuit diagram to generate the 2nd input of the full adder, A single stage arithmetic circuit to produce result of the operations on 1-bit is shown in figure-5:

Figure -5: Single stage of arithmetic unit

The operation of the single stage of the arithmetic unit is summarized in table below:

Selection Ci A B Operation Function
S1 S0
0 0 0 A 0 Transfer F=A
0 0 1 A 0 Increment F = A +1
0 1 0 A B Add F = A + B
0 1 1 A B Add with Carry F = A + B +1
1 0 0 A B’ A-B F = A + B’
1 0 1 A B’ 2’s complement subtraction F= A + B’ + 1
1 1 0 A 1 Decrement F = A-1
1 1 1 A 1 Transfer F= A+ All1’s+1

4-bit Arithmetic Circuit

We can now extend the above logic diagram to generate a 4-bit arithmetic circuit. We implement the 4-bit arithmetic unit by employing 4 full adders and co of the previous stage connected as the Cin of next stage adder. The complete design is shown in figure-6

Figure-6: A 4-bit arithmetic unit

Design of Logic Circuit

The logic circuit performs the logic operations on two operands. Let us assume that we wish to perform OR, AND, XOR and the NOT operation but one at a time, so the best choice for implementation is to use a 4×1 multiplexer. This is shown figure-7

Figure-7: Logical unit

The function table in figure-7 describes the operation of the above logical unit.

A complete Arithmetic and logic Unit

We can combine the arithmetic and the logic circuits discussed above to get the complete ALU. Since only one of the two operations. To select either an arithmetic or a logic operation we would require a 2×1 multiplexer. The block diagram of the complete ALU is shown figure-8:

Figure-8: Implementation of a complete ALU

Conclusion:

An ALU is a multi function combinational circuit that can perform number of operations on two N-bit numbers. An ALU can be very easily designed using the modular approach. An XOR gate can be used to implement a NOT function and hence act as a mode control input for performing 2’s complement addition subtraction. Logical unit is implemented using a 4×1 Mux to generate one of the four logical functions

 

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