Enumeration Type Digital Design using VHDL by Ravinder Nath Rajotiya - May 11, 2021May 11, 20210 Enumeration Type: Enumeration type is used when it is represent values that are required for a specific operation. All values in an enumeration are user defined and cannot be any one from predefined types. These values may be character literals or named identifiers. For examples we can use values as ‘0’,’1’…..’a’,’b’,c’……..ADD, SUB, MUL……. Note here that we cannot use the numeric values such as 0, 1 etc VHDL will give error during synthesis, but we are to use them as character literals as ‘0’ , ‘1’ . Syntax: TYPE TYPE_NAME is (value{,value}); BIT Type: A bit type object can hold value ‘0’ or ‘1’. It is an enumerate type defined in the std library. The syntax of BIT type as defined in std library
Data Types in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 10, 20210 Data Types in VHDL The syntax of object declaration as studied in the previous chapter is again revisited. Object_class Object_name : Object_data_type[:= Initial_value]; The essential component of the above declaration is object class and data type. Whereas the class signifies the class/category (signal, variable, constant, file) to which the object belongs, the data type gives an idea of the type (bit, Boolean, std_logic, integer etc.) -of the values an object may take and the value from a set of the values that an object may be assigned. Every given data type supports some specific operations for the object for example data type bit supports logical and arithmetic operations but std_logic (as given in std-logic_1164) does not support arithmetic operation. If arithmetic operation on std_logic