Loop statements are a catagory of control structures that allow you to specify repeating sequences of behavior in a circuit. The statement are used for iterating a well-defined task. In each iteration it then increaments or decrement some local identifier for use inside the LOOP statement. VHDL has following types of iterative statements i. FOR statement ii. WHILE statement iii. and infinite loops Syntax for the iteration statements: i. FOR statement [label :] FOR index in <range> LOOP Statement(s); End LOOP; Example-1: Synthesize a 4-bit Incrementer in sequential modelling in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity incrementer is generic(N: integer:=6); port ( a : in STD_LOGIC_VECTOR (N downto 0); b : out STD_LOGIC_VECTOR (N downto 0) ); end incrementer; architecture Behavioral of incrementer is begin process(a) variable x: std_logic_vector(N downto 0); begin b(0) <= NOT