Interfacing memory with 8086 microprocessor

To interface the memory with 8086, we need the system bus and the control signals for memory read and write operations. The system bus was generated by demultiplexing the A19/S6 —A16/S3 and AD15—AD0 lines using the latches such as 74373 thus giving us the address lines A19-A0 and data bus as D15-D0.

The IO and memory read and writes signals are generated from M/IO’, RD’ and Wr’ as shown in the table below. But for memory interfacing we will be using MEMR’ and MEMW’ signals for memory read and memory write:

Figure below shows the hardware circuit used to generate the memory read (MEMR’) and memory write (MEMW’) signals.

Generation of the Chip Select Signals

The chip select signals can be generated using:

i. Logic Gates

ii. Decoder (74LS138)

i. Assuming interfacing a total 16 KByte memory and If memory is to be organized as 8Kbyte odd and even memory banks then each chip will require 13-bit address lines. Rest of the 7 address lines can be connected to a AND gate for generating chip select signal as :

Chip Select using Decoder

Figure-3 gives the chip select signals as

Interfacing Hint:

1. Selecting the right memory chip
2. Finding the range of address for a chip
3. Logic for generating chip select signal
4. Logic for activating RD’ and WR’ signals for the memory

Example: Interface one 2Kx8 EEPROM and two 2Kx8 RAM chips with 8086 microprocessor allocating proper range of addresses for the ICs.