8255 Programmable Peripheral Interface Introduction:
8085 microprocessor need the interface ICs to interface with the I/O devices. In this lecture we focus on 8255 a programmable peripheral interface.
Features of 8255
40 pin IC.
24 I/O pins divided into 3 groups, Port-A, Port-B, and Port-C.
Port C can be used as a single 8-bit port or in group of four bits for providing handshake signals for Port-A and Port-B.
8255 can operate in different modes i.e. BSR Mode, and I/O Mode
BSR mode is used for controlling individual bits of port C in read/write operation,
I/O Mode of Operations are : Mode-0, Mode-1, Mode-2 .
Mode-0 is used when simple I/O activity is required on all three ports,
Mode-1 is used for handshake mode for Gp-A and G-B ports with handshake signals performed by Port-CL and Port-Cu.
Mod-2 is for bidirectional communication on Port-A with port-B in mode-0 or mode-1.
Since 8255 is a programmable device, it has an internal control word register which can be configured by writing a control word.
Internal Block Diagram of 8255
As seen in the block diagram, 8255 PPI contains the following components:
• Data Bus Buffer
• Read write control logic
• Group A and Group B control
• Ports- Group-A port, Group-B port
These are describe below:
- Data Bus Buffer:It is an 8-bit tri-state bi-directional buffer and is used to interface the 8255 to the system data bus. It is user to receive the control word or data from the CPU for the I/O device or from the I/O device through ports for sending to CPU. Control words and status information are also transferred through the data bus buffer
- Read/Write and Control Logic:
- The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.
- Chip Select(CS): A “low” on this input pin enables the communication between the 8255 and the CPU
- Read (RD): A “low” on this input pin enables 8255 to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the 8255.
- Write (WR): A “low” on this input pin enables the CPU to write data or control words into the 8255.
- Port Select 0 and Port Select 1(A0 and A1): These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1).
- Reset: A “high” on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode.
Figure-14.2: Port and Register Read/Write Signals
- Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the 8255. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 8255. Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports
- Ports The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the 8255. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both “pull-up” and “pull-down” bus-hold devices are present on Port A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B
Interfacing 8255 with 8085: