Instruction Cycle

In a digital computer the instructions are stored in the memory. When an instruction is executed it goes through a sequence of operations called an instruction cycle. The total time taken by the computer in executing an instruction is called an instruction cycle. It may contain different subcycle such as machine cycle.

An instruction under execution may take one or more machine cycle for its execution depending upon the format of the instruction. Figure shows the steps taken by an instruction during its execution. All these steps together constitute an instruction cycle.

Phases of Instruction cycle:

1. Fetch an instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory if the instruction has an indirect address.

4. Execute the instruction.

Sequencing the operations 

The program counter (PC) is initially loaded with the starting address first instruction

of a program. The sequence counter is initialized to ‘0’, there onwards, the sequence counter is incremented by ‘1’ and generates iming pulses T0, T1, T2, T3, T4……….

During each tick or pulse specified micro-operation take place.

Fetch and Decode Operation 

Step-1:

During first timing pulse T0, the AR is loaded with address from PC.

i.e.      T0 : AR <– PC

This is internally implemented as two sub micro-operations when the bus system get the input S2S1S0 = 010, these are:

T0 : BUS <– PC, AR <– BUS

this can be verified from figure that when the BUS get the control signal 010, PC contents is transferred to BUS and when T0 is active , then content of BUS is loaded in AR.

Step-2:

The instruction from the memory is transferred onto the BUS when the bus control signal is “111” Now when sequence timing pulse T1 is active, instruction is transferred to IR and PC incremented by ‘1’.. This is written in RTL as :

T1: IR <– M[AR], PC <– PC+1

Internally this miro-operation is implemented as :

T1: BUS <– M[AR],  IR <– BUS, INR PC

Step-3:

The instruction in IR is then decoded when the timing pulse T2 is active. This is shown by the following micro-operation:

T2 : D7, D6…….D0 <– Decode IR(14–12), I <– IR(15), AR <– IR(11–0)

At this time the type of instruction is identified so that the data prepation and execution of the instruction take place.

Flowchart of the Instruction Cycle:

The complete flowchart of the instruction cycle showing all four phases and the microoperations during each phase is shown in figure below:

 

Identification of Type of Instruction

As seen from the figure above, D7 along with the I bit plays the role of identifying the type of instruction.

D7 as high would indicate register or I/O related instruction whereas NOT D7 (i.e. D0- to D6) identifies the instruction as one of 7 memory related instruction.

D7 along with ‘I’ bit identifies the exact type of the instruction. The combination of D7 and I is shown in table below:

D7	I	Type of Instruction
0	0	Direct memory instruction
0	1	Indirect memory instruction,
1	0	I/O type instruction, such as INP, OUT
1	1	Register type instruction such as CMA, CLC, STC etc.

Execution phase of an instruction

Memory related instruction may be direct or indirect memory instruction.

(i) A direct memory intruction identified by D6 – D0 along with I=’0’. The address of operand is stored in AR during T2 decoding phase

(ii) An indirect memory intruction identified by D6 – D0 along with I=’1’. The address of operand is stored in AR during T3.

The execution also requires the data to be read/fetched during the T3 timing cycle and the execution starts during timing pulse T4

(iii) Register related and I/O related instructions is executed during T3 timing pulse

The micro-operations of all type of instructions is shown in table below:

Mnemonic	Decoder Operation	Mode Bit	Timing Pulse	Symbolic microoperations
AND logical AND	D0	0	T3, T4	D0T3 : NOP D0T4 : DR D0T5 : AC ∧ DR, SC
ADD Add Acc with DR	D1	0	T3, T4	D1T3 : NOP D1T4 : DR D1T5 : AC
LDA Load Acc	D2	0	T3, T4	D2T3 : NOP D2T4 : DR D2T5 : AC
STA Store Acc	D3	0	T3, T4	D3T3 : NOP D3T4: M [AR]
BUN Unconditional Branch	D4	0	T3, T4	D4T3 : NOP D4T4: PC
BSA Branch and save return address	D5	0	T3, T4	D5T3 : NOP D5T4: M[AR] AR+1 D5T5: PC
ISZ Branch, skip if zero	D6	0	T3, T4	D6T3 : NOP D6T4: DR D6T5 : DR D6T6 : M[AR]
CLA Clear Acc	D7	0	T3	D7I’T3O11: AC
CLE	D7	0	T3	D7I’T3O10: E
CMA	D7	0	T3	D7I’T3O9: AC AC’, SC
CME	D7	0	T3	D7I’T3O8: E E’, SC
CIR	D7	0	T3	D7I’T3O7: AC
CIL	D7	0	T3	D7I’T3O6: AC l AC, E
INC	D7	0	T3	D7I’T3O5: AC AC+1, SC
SPA	D7	0	T3	D7I’T3O4: If(AC(15)=0) then PC
SNA	D7	0	T3	D7I’T3O3: If(AC(15)=1) then PC
SZA	D7	0	T3	D7I’T3O2: If(AC=0) then PC
SZE	D7	0	T3	D7I’T3O1: If(E=0) then PC
HLT	D7	0	T3	D7I’T3O0: SSC
INP	D7	1	T3	D7IT3O5 : AC
OUT	D7	1	T3	D7IT3O4 : OUTR O– 0, SC
SKI	D7	1	T3	D7IT3O3 : If(FGI=1) the (PC
SKO	D7	1	T3	D7IT3O3 : If(FGO=1) the (PC
ION	D7	1	T3	IEN
IOF	D7	1	T3	IEN

Summary: The execution of an instruction goes through an instruction cycle during. Instruction cycle consist of fetch operation, decode of instruction, fetching the data and execution of instruction.  The I or the mode along with the decoded opcode D7 is used to identify the type of instruction.