Instruction Cycle


The programmer stores the program into the computer memory. When an program and hence an instruction is required to be executed inside the microprocessor, a number of micro-operations are generated. These include:

  1. Assigning memory address to the instruction to be read

  2. Reading the instruction

  3. Loading the instruction in the Instruction Register

  4. Generating address of the operands

  5. Reading the operands from the memory

  6. Loading the operands in the accumulator and data registers(DR)

  7. Loading the ALU with data

  8. Transferring the result to Accumulator

  9. Finally assigning the memory address for storing the result in memory

  10. Transferring the result at the memory location.

Thus we conclude that a program is executed by going through a cycle of number of micro-operations for each instruction. Each instruction cycle in is therefore is subdivided into a sequence of subcycles or phases

Phases of Instruction cycle:

1. Fetch an instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory if the instruction has an indirect address.

4. Execute the instruction.

The block diagram of figure-1 shows the data path of the first two phase of the instruction cycle that is the fetch and decode operation.

Figure-1 : Data path of 1st two phases of instruction cycle

1st Phase :- Fetch an Instruction: The fetch operation requires the MAR to be loaded with address of the instruction to be fatched, this is given in the PC. Therefore first operation is:

T0 : AR <– PC

How is this miro-peration implemented? Well this happens As:

BUS <– PC

AR <– BUS

2nd phase in fetch operation is to read the instruction from the address given in AR and increment the PC.This is given below:

T1: IR <– M[AR], PC <- PC+1

Again this miro-operation is implemented as :

BUS <– M[AR]

IR <– BUS

INR PC

Once the instruction has been read into the Instruction register (IR), then in the next timing cycle T2, it is required to be decoded. This operation is shown below.

T2: decode IR(14 -12), AR <– IR( 11 – 0) , M <– IR(15)

At this time the type of instruction is identified so that the data prepation and execution of the instruction take place.

Flowchart of the Instruction Cycle:

The complete flowchart of the instruction cycle showing all four phases anf the microoperations during each phase is shown in figure below:

During T0 : the AR is initialized with the content of PC

During T1: the instruction is fetched from memory in the IR

During T2, decoding of bits (14 – 12) of IR by 3×8 decoder, gives us D0 to D7 outputs indicating the type of the instruction.

D7 as high would indicate register or I/O related instruction whereas NOT D7 (i.e. D0- to D6) identifies the instruction as one of 7 memory related instruction.

D7 along with ‘I’ bit identifies the exact type of the instruction. The combination of D7 and I is shwn in table below:

D7

I

Type of Instruction

0

0

Direct memory instruction and the execute micro-operation is:

T3: NOP

T4: execute instruction, SC<–0

0

1

Indirect memory instruction,

T3 : AR <– M[AR]

T4 : execute instrcution, SC <–0

1

0

I/O type instruction, such as INP, OUT

T3: execute instruction, SC <–0

1

1

Register type instruction such as CMA, CLC, STC etc.

T3 : execute instruction, SC <–0

Micro-operation for execute phase of an instruction

Memeory related instruction may be direct or indirect memory instruction.

(i) A direct memory intruction identified by D6 – D0 along with I=’0’. The address of operand is stored in AR during T2 decoding phase

(ii) An indirect memory intruction identified by D6 – D0 along with I=’1’. The address of operand is stored in AR during T3.

Execution of memory related (both direct or indirect) instruction the execution starts during timing pulse T4

Register related and I/O related instructions is executed during T3 timing pulse

The micro-operations of all type of instructions is shown in table below:

Mnemonic

Decoder Operation

Mode Bit

Timing Pulse

Symbolic microoperations

AND

logical AND

D0

0

T3, T4

D0T3 : NOP

D0T4 : DR <- M[AR]

D0T5 : AC <- AC ∧ DR, SC <- 0

ADD

Add Acc with DR

D1

0

T3, T4

D1T3 : NOP

D1T4 : DR <- M[AR]

D1T5 : AC <- AC + DR, SC <- 0

LDA

Load Acc

D2

0

T3, T4

D2T3 : NOP

D2T4 : DR <- M[AR]

D2T5 : AC <- DR, SC <-0

STA

Store Acc

D3

0

T3, T4

D3T3 : NOP

D3T4: M [AR] <-AC, SC <-0

BUN

Unconditional Branch

D4

0

T3, T4

D4T3 : NOP

D4T4: PC <- AR, SC <- 0

BSA

Branch and save return address

D5

0

T3, T4

D5T3 : NOP

D5T4: M[AR] <- PC, PC <- AR+1

D5T5: PC <- AR, SC <- 0

ISZ

Branch, skip if zero

D6

0

T3, T4

D6T3 : NOP

D6T4: DR <- M[AR]

D6T5 : DR <- DR +1

D6T6 : M[AR] <- DR, If (DR = 0) then (PC <- PC+1), SC<-0

CLA

Clear Acc

D7

0

T3

D7I’T3O11: AC <- 0, SC <-0

CLE

D7

0

T3

D7I’T3O10: E <- 0, SC <-0

CMA

D7

0

T3

D7I’T3O9: AC <- AC’, SC <-0

CME

D7

0

T3

D7I’T3O8: E <- E’, SC <-0

CIR

D7

0

T3

D7I’T3O7: AC <- Shr AC, AC(15)<-E, E<- AC(0), SC <-0

CIL

D7

0

T3

D7I’T3O6: AC <- Shl AC, E< -AC(15), AC(0)<- E, SC <-0

INC

D7

0

T3

D7I’T3O5: AC <- AC+1, SC <-0

SPA

D7

0

T3

D7I’T3O4: If(AC(15)=0) then PC<-PC+1, SC <-0

SNA

D7

0

T3

D7I’T3O3: If(AC(15)=1) then PC<-PC+1, SC <-0

SZA

D7

0

T3

D7I’T3O2: If(AC=0) then PC<-PC+1, SC <-0

SZE

D7

0

T3

D7I’T3O1: If(E=0) then PC<-PC+1, SC <-0

HLT

D7

0

T3

D7I’T3O0: S<- 0, SC <-0; S is start-stop FF

INP

D7

1

T3

D7IT3O5 : AC<- INPR, FGI<- 0, SC<-0

OUT

D7

1

T3

D7IT3O4 : OUTR <- AC, FGO0, SC<-0

SKI

D7

1

T3

D7IT3O3 : If(FGI=1) the (PC<-PC+1), SC<-0

SKO

D7

1

T3

D7IT3O3 : If(FGO=1) the (PC<-PC+1), SC<-0

ION

D7

1

T3

IEN <- 1, SC <-0

IOF

D7

1

T3

IEN <- 0, SC <-0

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