Design of Comparator in VHDL VHDL Lab by Ravinder Nath Rajotiya - August 11, 2019August 11, 20190 Share on Facebook Share Send email Mail Print Print Table of Contents Toggle AIM:Objective:Theory:The equations are :Dataflow Modeling ComparatorSimulationBehaviour ModelingStructure Modeling2-bit comparator AIM: Write a VHDL program for a comparator and check the wave forms and the hardware generated Objective: To understand the working of Comparator To learn VHDL codin To understand functional simulation Theory: A comparator is a combinational circuit that compares two objects and returns the outcome as “equal”, “less then”, or “greater then”. The entity comparator is shown below Figure: Comparator Symbol The truth table is given below: INPUTS OUTPUTS a b LT GT EQ 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 The equations are : EQ = a’.b’ + ab à a xnor b i.e. EQ <= ‘1’ when a=b LT = a’b i.e LT <= ‘1’ when (not a and b) GT = ab’ i.e GLT <= ‘1’ when (a and (not b)) VHDL Code for Comparator Dataflow Modeling Comparator CONCURRENT Code for 1-bit comparator Design in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator is Port ( a : in STD_LOGIC; b : in STD_LOGIC; lt : out STD_LOGIC; gt : out STD_LOGIC; eq : out STD_LOGIC); end comparator; architecture Behavioral of comparator is begin lt<= ‘1’ when a < b else ‘0’; gt<= ‘1’ when a >b else ‘0’; eq<= ‘1’ when a = b else ‘0’; end Behavioral; Simulation Figure: Simulation of a comparator Behaviour Modeling Behavioral Code for 1-bit comparator Design in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator is Port ( a : in STD_LOGIC; b : in STD_LOGIC; lt : out STD_LOGIC; gt : out STD_LOGIC; eq : out STD_LOGIC ); end comparator; architecture Behavioral of comparator is begin Process (a,b) Begin If (a < b) then L <= ‘1’; Elsif (a > b) then G <= ‘1’; Else Eq<= ‘1’; End if; End process; End; Structure Modeling Structural Design for 1-bit Comparator in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator is Port ( a : in STD_LOGIC; b : in STD_LOGIC; lt : out STD_LOGIC; gt : out STD_LOGIC; eq : out STD_LOGIC ); end comparator; architecture Behavioral of comparator is component AND_GATE port( a, b: in std_logic; c: out std_logic); end component; component XOR_GATE port( a, b: in std_logic; c: out std_logic); end component; component NOT_GATE port( a : in std_logic; b : out std_logic); end component; begin – – — – 2-bit comparator Two bit ComparatorBehavioural Modeling Library ieee; Use ieee.std_logic_1164.all; entity comp is Port ( a : in STD_LOGIC_VECTOR (1 downto 0); b : in STD_LOGIC_VECTOR (1 downto 0); eq : out STD_LOGIC; l : out STD_LOGIC; g : out STD_LOGIC ); end comp; architecture Behavioral of comp is begin process(a,b) begin if(a<b) then L <= ‘1’; else l <= ‘0’; end if; if(a>b) then G <= ‘1’; else G <= ‘0’; end if; if(a=b) then eq<= ‘1’; else eq<= ‘0’; end if; end process; end Behavioral; Share on Facebook Share Send email Mail Print Print