Design of Code Converters in VHDL

AIM:

CODE CONVERTERS IN VHDL

Objective:

  1. To revise the basic theory behind the working of the Code Converters
  2. To synthesize and simulate using VHDL

Theory of Code Converters:

We, in our day-to-day life deal with numerous forms of data, it can be decimal digits and numbers, alphabets and string or even the special symbol e.g your country currency symbol. We represent this data using code for the computer to process and transmit. As the computer or any other electronic machine does not understand these data patterns, we need to convert them into a form suitable for these machines to understand. The one commonly employed is the binary number system.

We also see the real images around us, but when we need to transmit the same at a distant place (as is the case in TV transmission), the image is not transmitted as it is, it is first converted into the binary pattern and then transmitted. At the receiving end the binary format is again converted into an image for view purpose.

When you speak into the cellular phone, an encoder converts the sound of your voice into electrical signals — which can travel very fast over very long distances. When the electrical signals get to your friend’s cellular phone, a decoder converts the electrical signals back to the sound of your voice! So now you know: Code converters are used for more than protecting private information from spies.

One is for the security reasons only you know the conversion nobody else knows the conversion so that may be a good enough reason it is called encryption.

We convert from one type of code to other type of code, sometimes for convenience, sometimes for security reasons you may want to have a code and you don’t want somebody to understand so you have a key and only you know the key so you convert those numbers using that key to another set of numbers and use it. We also want to do it for some hardware reasons. Sometimes by having a particular representation of 0s and 1s in a particular way the patterns of 0s and 1s falls in a particular pattern and the hardware implementation become simpler. There are numerous type conversions, some of them are:

  • BINARY to GRAY code converter
  • GRAY to BINARY code converter
  • BCD to XS-3 code converter
  • BCD to Seven segment code converter

The above conversion are discussed one by one and are synthesized using VHDL in the following paragraphs.

 Synthesis of Code Converters in VDSL

Binary-to-Gray

BINARY to GRAY code converter

 Concurrent style of modelling for binary to gray code converter

The binary to gray code conversion is shown in the following table:

Binary Gray
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

 

 

We observe that G2 is same as B2

G1= ∑m (2,3, 4, 5); solving we get G1 = B2 xor B1

G0 = ∑m (1, 2, 5, 6); solving we get G0 =B1 xor B0

 

The simplified logic diagram for the binary to gray is shown in figure below

 

Figure: Binary to Gray

The VHDL code for a 4 bit binary gray code conversion is shown below:

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity btog is

Port (

b : in  STD_LOGIC_VECTOR (3 downto 0);

g : out  STD_LOGIC_VECTOR (3 downto 0)

);

end btog;

architecture dataflow of btog is

begin

G(3) <= B(3);

G(2) <= B(3) xor B(2);

G(1) <= B(2) xor B(1);

G(0) <= B(1) xor B(0);

end dataflow;

 

Structure Style

Structure style modelling for binary to gray code conversion using concurrent GENERATE statement

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity btog is

Port (

b : in  STD_LOGIC_VECTOR (3 downto 0);

g : out  STD_LOGIC_VECTOR (3 downto 0));

end btog;

architecture struct_model of btog is

begin

G(3) <= B(3);

LOOP1 : for i in 0 to 2 GENERATE

Bi : XOR_GATE port map

(

B(i), B(i+1), G(i)

);

END GENERATE;

end struct_model;

Alternate way of coding:

architecture Behavioral of btog_struct is

signal X : std_logic_vector(4 downto 1);

begin

X(4) <= ‘0’;

X(3 downto 1) <= B(3 downto 1);

LOOP1 : for i in 0 to 3 GENERATE

Bi : entity work.xor_gate port map

(

B(i), X(i+1), G(i)

);

END GENERATE;

 ——————————————————-

 

Behaviour Modeling

 –a 4-bit binary to gray code converter using sequential modelling

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity bin_to_gr is

generic(N: integer:=3);

Port (

b : in  STD_LOGIC_VECTOR(3 downto 0);

g : out  STD_LOGIC_VECTOR(3 downto 0));

end bin_to_gr;

 

architecture Behavioral of bin_to_gr is

begin

process(b)

begin

g(3) <= b(3);

fori in 0 to 2 LOOP

if B((N-1)-i) = B(N-i) then

g((N-1)-i) <= ‘0’;

else

g((N-1)-i) <= ‘1’;

end if;

end LOOP;

end process;

end Behavioral;

  

BCD to XS-3

 

VHDL code for BCD to XS-3 code conversion

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

useieee.std_logic_unsigned.all;

entity btog is

Port (

b : in  STD_LOGIC_VECTOR (3 downto 0);

g : out  STD_LOGIC_VECTOR (3 downto 0)

);

end btog;

architecture Behavioral of btog is

begin

process(b)

begin

if (b <10) then

g <= b+3;

else

g <= “ZZZZ”;

end if;

end process;

end Behavioral;

 

BCD to 7-segment

VHDL Code for BCD to 7-segment Conversion

Figure: BCD-7segment Decoder and 7 Segment Display interfacing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_arith.ALL;

entity bcd_to_7seg is

Port (

bcd : in  STD_LOGIC_VECTOR (3 downto 0);

Seven_seg : out  STD_LOGIC_VECTOR (6 downto 0));

end bcd_to_7seg;

architecture Behavioral of bcd_to_7seg is

begin

seven_seg  <=     “1111110” when bcd = “0000” else

“0110000” when bcd = “0001” else

“1101101” when bcd = “0010” else

“1111001” when bcd = “0011” else

“0110011” when bcd = “0100” else

“1011011” when bcd = “0101” else

“1011111” when bcd = “0110” else

“1110000” when bcd = “0111” else

“1111111” when bcd = “1000” else

“1110011” when bcd = “1001” else

Others=>’Z’ when others;

end Behavioral;

Figure: BCD-to-7segment Conversion Simulation

 

Updated: August 12, 2019 — 5:53 am

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