AIM :
Design of Flip-Flops in VHDL
Objective:
- To revise the basic theory behind the working of the flip flops
- To understand the syntax of VHDL
- To synthesize and simulate using VHDL
Theory:
The theory extend from latches to flip-flops. the basic similarity and differences between a latch and a flip-flop being:
| Sl | Latch | Flip-Flop |
| 1 | It is a 1-bit memory element | It is also a 1-bit memory element |
| 2 | It is event based | It is clock based |
| 3 | Asynchronous operation | Synchronous operation |
| 4 | Operates n level triggered of enable /clock signal | Operates triggering at edges of clock signal |
| 5 | VHDL sytax :
if clock=’1’ then D <= ‘1’; else D <=’0’; end if; |
VHDL Syntax:
If CLK’EVENT AND CLK=’1′ THEN If D=’1’ then Q <= ‘1’; Qbar <= ‘0’; Else Q<=’0’; Qbar<=’1’; End if; |
A flip-flop is used as a one bit storage element in the digital systems. The flip-flops are of various types as given below:
- SR Flip-Flop
- D Flip Flop
- T Flip-Flop
- JK Flip-Flop
Synthesized of Latch and Flip-Flops in VHDL
[tabby title=”D Latch”]
D Latch
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_latch is
Port (
d : in STD_LOGIC;
clock : in STD_LOGIC;
q : out STD_LOGIC;
q_bar : out STD_LOGIC
);
end d_latch;
architecture Behavioral of d_latch is
signal x : std_logic;
begin
process(x,d, clock)
begin
if (clock=’1′) then
x <= d;
end if;
q <= x;
q_bar<= not x;
end process;
end Behavioral;
Simulation of D-Latch
[tabby title=”SR Flip-Flop”]
SR Flip-flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sr_ff is
Port (
RST : IN STD_LOGIC;
S : in STD_LOGIC;
R : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
Q_BAR : out STD_LOGIC
);
end sr_ff;
architecture Behavioral of sr_ff is
SIGNAL TMP, TMP_BAR: STD_LOGIC;
begin
PROCESS (RST, TMP,TMP_BAR,S,R,CLK)
BEGIN
IF (RST=’0′ ) THEN
TMP <= ‘0’;
TMP_BAR <= ‘1’;
ELSIF CLK’EVENT AND CLK=’1′ THEN
IF (S /= R) THEN
TMP <= S;
TMP_BAR <= R;
ELSIF (S=’0′ and R=’0′) THEN
TMP <= TMP;
TMP_BAR <= TMP_BAR;
ELSE
TMP <= ‘Z’;
TMP_BAR <= ‘Z’;
END IF;
END IF;
Q <= TMP;
Q_BAR <= TMP_BAR;
END PROCESS;
end Behavioral;
Simulation of SR Flip-Flop
Figure: Simulation of SR Flip-Flop
[tabby title=”D Flip-Flop Synchronous”]
D Flip-Flop:
The D-Flip-Flop code given below uses clock’even in the architecture. This will synthesize a synchronous D-Flip-Flop. It also requires the use of the sensitivity list which is part of process statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_FF is
Port (
d : in STD_LOGIC;
clock : in STD_LOGIC;
q : out STD_LOGIC;
q_bar : out STD_LOGIC
);
end D_FF;
architecture Behavioral of D_FF is
signal x : std_logic;
begin
process (x,clock)
begin
if ( clock’event and clock = ‘1’ ) then
x <= d;
end if;
q <= x;
q_bar<= not x;
end process;
end Behavioral;
In the above code if the sensitivity list was not assigned, the compiler will through a warning One or more signals are missing in the process sensitivity list. If we skip the sensitivity list, there is yet another way of writing the correct code using WAIT UNTIL as given below:
[tabby title=”D Flip-Flop Asynchronous”]
The asynchronous design does not use the sensitivity list in the process statement. If we skip the sensitivity list, there is yet another way of writing the correct code using WAIT UNTIL as given below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff_asynch is
Port (
d : in STD_LOGIC;
clock : in STD_LOGIC;
q : out STD_LOGIC;
q_bar : out STD_LOGIC
);
end d_ff_asynch;
architecture Behavioral of d_ff_asynch is
signal x : std_logic;
begin
process
begin
WAIT UNTIL clock’EVENT and clock=’1′;
x <= d;
q <= x;
q_bar<= not x;
end process;
end Behavioral;
———————————————————————–
Synthesis of D-FF with asynchronous reset
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff_async is
Port (
D : in STD_LOGIC;
RST : in STD_LOGIC;
CLOCK : in STD_LOGIC;
Q : out STD_LOGIC;
Q_BAR : out STD_LOGIC
);
end d_ff_async;
architecture Behavioral of d_ff_async is
SIGNAL X : STD_LOGIC;
begin
PROCESS (X,RST, CLOCK)
BEGIN
IF RST=’0′ THEN
x <= ‘0’;
ELSIF CLOCK’EVENT AND CLOCK = ‘1’ THEN
X <= D;
END IF;
Q <= X;
Q_BAR <= NOT X;
END PROCESS;
end Behavioral;
Simulation of Asynchronous Type D Flip-Flop
Figure: Simulation of D Flip-Flop
[tabby title=”JK Flip-Flop”]
JK flip-flop
entity JK_FF is
Port (
j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC
);
end JK_FF;
architecture Behavioral of JK_FF is
signal temp : std_logic;
signal sel: std_logic_vector(1 downto 0);
begin
sel <= j&k;
process (temp, sel ,clk)
begin
if clk’event and clk=’1′ then
case sel is
when “00” => temp <= temp;
when “01” => temp <= ‘0’;
when “10” => temp <= ‘1’;
when “11” => temp <= not temp;
when others => temp <= ‘Z’;
end case;
Q <= temp;
end if;
end process;
end Behavioral;
Simulation of JK Flip-Flop
Figure: Simulation of JK Flip-Flop
[tabbyending]
