Introduction to  Counters

I remember my childhood, at a time even before going to the primary school, we used to play with pebbles, soon we started counting the pebbles. When I joined school, I realized that counting is part of our life and is used in every walk of life, count starting from zero, or starting from any number (preset). As I grew, I found counting used for different purpose; we go to refuel our vehicle, there a meter that counts the amount and the quantity of fuel; counting the marks awarded to student in an exam; days temperature, population of a city/ country, counting the score in a match, number of votes obtained by a candidate in an election, number of bottles filled in a plant, and so on.

In this chapter we will study the design of the digital counters. A digital counter is a sequential circuit consisting of a number of flip-flops connected in some suitable manner to count the sequence of pulses / events applied to it. Counters can be of the following types:

1. Synchronous and Asynchronous clocks
2. Single and Multi-Mode Counters (Up counter, Down Counter, Up-Down Counter)
3. Modulus Counter: Modulus-3, Modulus-6, Modulus-10 etc.
4. Shift register counters:- Ring Counter, Johnson Counter etc.

The counter like a register is a sequential circuit. The sequential circuit can be a synchronous or an asynchronous circuit. In synchronous all the internal block of the circuit operate in synchronous with a clock pulse, whereas in asynchronous circuit these block are not synchronized to any common clock but instead each internal block get a clock pulse from different sources.
The single and multimode counters are used for single mode that is either up or down counter or multi-mode counter as up/down counter. The modulus counter on the other hand are the counters that count up to a certain count, a counter that counts 0 through 9 is Modulus-10 counter, Its name come from the number of states that it counts. So we have different modulus counters as mudulus-3, modulus-6, modulus-10.

So we find counters are of different type and are one of the many applications of sequential logic that has a widespread use from simple digital alarm clocks to computer memory pointers. Also the registers and counters belong to the category of MSI sequential logic circuits having similar architecture, that both use a cascaded arrangement of more than one flip-flop with or without combinational logic devices. The registers and the counters are found as a very important building block of sequential logic.

Applications of Counters:

Counters are part of every digital system, and are used for:

1. in counting applications.
2. To measure the time interval between two unknown time instants
3. To measure the frequency of a given signal
4. Counters are useful for digital clocks and timers
5. Used in oven timers, VCR clocks, etc.

Asynchronous Counters:
Asynchronous counter are the simplest to design, each flip-flop in this type of counters get their clock pulses from different source. Figure- shows an asynchronous ripple counter. The second flip-flop in figure-   get is clocked by Q1 output of the first flip-flop,  3rd FF is clocked by Q2 output of 2nd FF and so on.

 Figure-1 Asynchronous Ripple Counter

Operation

Assuming that initially all the flip-flops are in reset state that is Q1=Q2=Q3=Q4 =0, the inputs J1 and J2 are tied to Vcc i.e J1=K1=1.  Now when the first clock input strikes the the first FF, it will toggle at the falling edge (-ve going ) of this clock input, thus making the output Q1 to go high. When the clock goes high there will not be any change in the output.

Output Q1 drive the clock input of the 2nd FF, since both J2 and K2 are tied to Vcc, it will toggle on the next (2nd) -ve going clock pulse.
Output Q2 drives clock input to the 3rd FF, J3 and K3 both being tied to Vcc will toggle on the -ve going clock input (which is Q2)
Similarly, Q3 drives the clock input of 4th FF which will also toggle on the -ve going clock input(which is Q3).

The complete behavior is depicted in the waveform given in figure- As seen every time the clock to each FF take a transition from high to low, the respective FF toggle to change the state. Thus Q1 toggle every time CLK input to 1st FF take a high to low transition. Q2 toggles every time Q1 goes from high to low. Q3 toggle evrytime Q2 goes from high to low, and finally Q4 change state (toggle) when there is a transition from high to low in Q3 which is acting as clock input to the 4th FF.

 

 

Figure-2 : Ripple Counter Waveform

Ripple Down Counter:

A binary counter with a reverse count is called a binary down-counter. The count is decremented by ‘1’ with every clock pulse. A counter will work as a ripple binary down-counter is the output is taken  from the Q’ terminal of all the flip-flops.  The operation of the down-counter is described as-

1. All the flip-flops toggle on the +ve edge of the clock pulse, however if the –ve edge-triggered flip-flops are used then CLK input must be connected to the Q’ of the previous flip-flop.
2. Lowest order bit must be complemented with every clock pulse.
3. Any other bit in sequence is complemented if the previous lower-order bit goes from ‘0’ to ‘1’

 

Design of Counters

Sequential-Synchronous Counter Design

The different steps for the design of the synchronous sequential circuits are:
i)          State diagram

1. ii)         state table

iii)        excitation table

1. iv)        Simplification using K-Map
2. v)         Logic Design

Example-1: Design a 4-bit synchronous up counter using T flip-flops

Present State	Next State	Excitation
Q1Q2Q3Q4	Q1Q2Q3Q4	T1	T2	T3	T4
0  0  0  0	0   0  0 1	0	0	0	1
0  0  0  1	0  0  1  0	0	0	1	1
0  0  1  0	0   0  1  1	0	0	0	1
0  0  1  1	0  1  0  0	0	1	1	1
0  1  0  0	0  1  0  1	0	0	0	1
0  1  0  1	0  1  1  0	0	0	1	1
0  1  1  0	0  1  1  1	0	0	0	1
0  1  1  1	1  0  0  0	1	1	1	1
1  0  0  0	1  0  0  1	0	0	0	1
1  0  0  1	1  0  1  0	0	0	1	1
1  0  1  0	1  0  1  1	0	0	0	1
1  0  1  1	1  1  0  0	0	1	1	1
1  1  0  0	1  1  0  1	0	0	0	1
1  1  0  1	1  1  1  0	0	0	1	1
1  1  1  0	1  1  1  1	0	0	0	1
1  1  1  1	0000	1	1	1	1

 

Figure-2: K-Map Solution for T1, T2, T3, T4

The K-Map Simplification for T1, T2, T3, T4 leads to following simplified logic equations.

T1=Q2Q3Q4
T2= Q3Q4
T3=Q4
T4=1

Logic Diagram for the 4-bit binary up counter is given below:
Figure-3: Logic Diagram of Synchronous Up Counter

 

Example :Deign a3-bit Binary up/Down Counter

Figure-4: State Diagram of 3-bit Up/Down Synchronous Counter

Control  Input	State		Excitation
x	Present State Q1Q2Q3	Next State Q1Q2Q3	T1	T2	T3
0	0 0 0	0 0 1	0	0	1
0	0 0 1	0 1 0	0	1	1
0	0 1 0	0 1 1	0	0	1
0	0 1 1	1 0 0	1	1	1
0	1 0 0	1 0 1	0	0	1
0	1 0 1	1 1 0	0	1	1
0	1 1 0	1 1 1	0	0	1
0	1 1 1	0 0 0	1	1	1
1	0 0 0	1 1 1	1	1	1
1	0 0 1	0 0 0	0	0	1
1	0 1 0	0 0 1	0	1	1
1	0 1 1	0 1 0	0	0	1
1	1 0 0	0 1 1	1	1	1
1	1 0 1	1 0 0	0	0	1
1	1 1 0	1 0 1	0	1	1
1	111	1 1 0	0	0	1

Figure-5: K-Map Simplification for Up Down Counter

Figure -Logic Circuit