Introduction

The second type of digital circuitry are the sequential circuits. These circuitry are formed as a combination of combinational and the memory element. The memory element stores the state of the circuit. We start discussing on Latches and Flip-Flops.

Latches

Storage elements that operate with signal levels (i.e. level triggered of signal input) are termed as latches. A latch is a bi-stable element having two states Q and Q’. It is a sequential circuit that will continuously change its state as soon as the input changes without waiting for the clock signal. A latch usually has an enable input. When the enable is active the output changes as soon as there is a change in the inputs. Latches are not of practical use in synchronous circuits. They are useful for asynchronous sequential circuits.

Basic SR Latch:

Figure below shows two ways of constructing a latch; 1^st using NOR gates, and 2^nd using NAND gates.

The NOR Latch outputs Q and Q’ can be expressed using the Boolean equations :

Q= (R + Q’)’    and Q’ = (S + Q)’

Operation of basic SR Latch

The operation of the NOR and NAND gate latch is summarized in the table below:

NOR Gate  Latch					NAND Gate  Latch
S	R	Qn	Remarks		S’	R’	Qn	Remarks
0	0	Qn	No Change		0	0	?	Forbidden; Must be avoided
0	1	0	Reset to ‘0’		0	1	1	Set
1	0	1	Set to ‘1’		1	0	0	Reset
1	1	?	Must be avoided		1	1	Qn	No Change

Flip-Flops

They are also known as bi-stable multi-vibrators. It is a basic memory element to store 1-bit of information. They have two stable states a ‘1’ and a ‘0’.These are controlled by edge-triggered transitions of clock pulse.

Flip-flop Switching Times

In designing the circuits the following timing parameters are of most important:

1. Set-up Time
2. Hold Time
3. Propagation Time

1. Set-up time: The minimum amount of time required for the data input to be present before the arrival of the clock puls.
2. Hold-time: The minimum amount of timethat the data input to be present after the application of the clock pulse
3. Propagation time: The amount of time it takes for the output to change state after an input trigger. For example:

If tset-up = 50 ms       t hold = 5ms, then the data bit has to be input at least 50 ms before the clock arrivaes and hold at least 5ms after the clock edge.

Triggering of the flip-flop:

The flip-flop triggering is of following types:

1. +ve edge trigger
2. -ve edge-trigger
3. Level trigger

 

Positive(+ve)edge triggered FF:

These FF set or reset at the +ve (or rising or leading) edge of the clock pulse depending on the state of the input signal and the output remain stable for 1 clock period. Symbolically such types of FF are identified by an arrow at the clock input.

Negative(–ve) edge triggered flip-flops

These FF set or reset at the -ve (or falling or trailing) edge of the clock pulse depending on the state of the input signal and the output remain stable for 1 clock period. Symbolically such types of FF are identified by a bubble or NOT gate at the clock input.

Level triggered flip-flops:

Level triggering means that the specified action occurs based on the steady state value of the input. That is when a certain level is reached a ‘0’ or a ‘1’ level.

Types of FF

1. SR FF
2. D FF
3. JK FF
4. T FF
5. Master Slave FF

SR Flip-Flop

An SR flip-flop can be drawn by modifying the basic SR Latch. Figure below shows an edge triggered SR flip-flop using NOR and NAND gates.

Characteristic Table of SR Flip-Flop

CLK	S	R	Qn	Remarks
0	x	x	Qn	No Change
1	0	0	Qn	No Change
1	0	1	0	Reset
1	1	0	1	Set
1	1	1	?	Indeterminate

The differentiator provides positive spikes corresponding to the leading edge of the clock pulse. Therefore the SR flipo-flop will be enabled for a short duration of the time when the +ve spike is present. The behaviour of the SR flip-flop is summarized below:

• With +ve edge of the pulse when S=R= 0 No change in the state of flipflop
• With +ve edge of the pulse when S= 0, R= 1; The FF sets to ‘1’i.e. goes to state ‘1’
• With +ve edge of the pulse when S= 1,R= 0; The FF resets i.e foes to state ‘0’.
• With +ve edge of the pulse when S= R= 1; The FF state is indeterminate

D Flip-Flop

It is formed by modifying a basic SR flip-flop by using a NOT (inverter) at the input that connects between the S and R inputs. Figure below shows the D FF formed using the NOR and NAND gates.

The table below summarizes the operation for both types (NAND and NOR) of of the D latches. As is evident from the figure (a) a NOR-D Latch, that when the clock goes high, the output Q depends on the D input. That is, for a high (1) clock, if the D input is low, Q=0, else if the D=1, then output Q=1. This fact is also shown in the truth table.

 

CLK	D	Qn (Present state)	Qn+1 (Next state)	Remarks
	x	Qn		No Change
	0	0	0	Reset
	0	1	1	Reset
	1	0	1	Set
	1	1	1	Set

Advantage: There is no indeterminate state hence the race problem is found to be fully eliminated

On analyzing the figure (b) above for the D latch using NAND gate, it is observed that for a high CLK, if D=0, S’=1 and R’=0 so output Q=0, also with the CLK=1, if D=1, then S’=0 and R’=1 so the Q is set i.e. Q=1. These facts are also shown in the NOR and the NAND latch waveform shown in figure (a) and figure (b).

Edge Triggered Flip-Flop

As seen in the preceding paragraph that flip-flop/latch changes its state during the positive-level triggered or negative level-triggered clock pulse. This type of triggering makes the output change more than once or many times for changes in the inputs. So we are required to keep the input stable during the whole clock pulse. Another method is to make the clock pulse very small, by making the RC time constant much smaller than the clock pulse-width.

Making the RC time constant much smaller make the capacitor to charge     Figure-3 shows the edge triggering circuit. In edge-triggered FF, the flip-flop changes its state at the rising or the falling edge of the clock pulse. For this a square wave clock pulse is applied to a differential circuit which gives pulse which are sharp rising / falling at the edges depending on the RC time constant. The edge-triggering will avoid the multiple changes in state during the same clock when the input changes many times.

In practice, the RC circuit is not used for generating the edge triggered pulse because the capacitors are difficult to manufacture on chip, instead other method such as direct coupled edge-triggering which employs the NAND gate circuit for generating the edge triggering. The direct coupled circuit is however not discussed in this learning material.

Edge Triggered D Flip-Flop

 

Figure-10 shows an edge triggered D flip-flop. The operation of the edge triggered D flip-flop is similar to the one described earlier for a D latch. The difference being the changes at the output can occur only during the rising edge or falling edge depending on whether the flip-flop is positive edge triggered or negative edge triggered.
Figure shown above is a +ve edge-triggered D flip-flop. Various cases for understanding the operation are:

case-1: When the clock pulse is falling down, then irrespective of the D input, output of the AND gates will be low, thus there is no change in the state of the D flip-flop.
Case-2: When the clock pulse rising high, now if D=0, the upper AND gate will produce a high output and the lower AND gate will produce a low output. This will reset the D flip-flop.
Case-3: On the rising edge of the clock pulse, if the D input goes high, the AND will produce a high for the lower NOR gate and a low for the upper NOR gate, this input will set the D flip-flop i.e. A low or 0 is stored in the flip-flop.
The advantage of D flip-flop is that the forbidden / indeterminate state as in SR when S=R=1 does not arise. Thus the D flip-flop gives only a valid state that either set or reset that is either it stores a ‘0’ when input D=0 or stores a ‘1’ when D.
Edge-triggered JK Flip-flop

Again the edge-triggered JK flip-flop will change state at the edge of the clock-pulse, that is at the rising or falling edge of the +ve edge-triggered or -ve edge-triggered JK flip-flop. For the purpose of discussion we assume a +ve edge-triggered JK flip-flop. The various case for the are discussed in the following paragraph and shown for conveneinece in the truth table.

Case-1: When the clock is low, irrespective of the J and K input, the state at the output (Q and Q’) does not change.

Case-2: When the input J=K=0, then also there is no change in state of the flip-flop.
Case 3: When J=1, K=0, then on the rising edge of the clock pulse the JK flip-flop will set to 1 that is the output Q=1.

Case 4: When J=0, K=1, then on the rising edge of the clock pulse the JK flip-flop will reset, that is the output Q=0.

Case 5: When J=1, K=1, then on the rising edge of the clock pulse the JK flip-flop will toggle (output Q will get complemented) that is if Q was earlier 0 then it will become 1 and vice-versa. These different states are shown in the waveform shown in figure-6

Anomaly in flip-flop operations and its solution

As seen earlier, when a change in an input variable is generated when the clock is high/ asserted, the basic cell in a flip-flop can change from the state stored into it on the rising edge, presenting anomaly. If this anomaly takes place, erratic machine behaviour will result. This means that multi-state change will occur during a single clock pulse.

There are two obvious solutions to this problem:
(a) Use narrow edge-triggered clock pulse.

(b)       Use a flip-flop that exhibit some sort of blocking operation that is use master / slave flip-flop which triggers on the falling-edge of the clock waveform and in turn blocks the changing data from modifying its output.

Master Slave JK Flip-Flop:

This flip-flop is designed specifically to avoid the dual mode anomaly allowing for its use in finite-state machine designs under certain constraints.

 

In a master/slave the slave device always follows the action of the master. During the positive or the rising edge of the clock pulse, the master cell is loaded in accordance with the J, K, Q and Q’ conditions. During the complete high period of the clock, the slave device is inhibited. On the falling edge or when the clock is low the data stored in the master is transferred to the slave and the output is updated. The final change in state occurs during the falling edge of the clock pulse. This is the reason the master / slave flip-flop is called pulse-triggered FF.
Case 1: When the output reset that is Q = 0 and Q’ =1 and the high clock arrives, While the clock is high, if J=1 and Q=0, the master FF will be set. During the falling edge of the clock pulse, this high output of master will set the slave Q output.
Case 2: If the flip-flop output is set, that is, Q=1, and the high clock pulse arrive, now while the clock is high, if J=0 and K=1, the output of master will reset, and during the negative or falling edge of the clock pulse, this will reset the final output. That is Q=0 and Q’ = 1.

Thus we find that the anomaly of pulse triggered flip-flop is avoided in master /slave flip-flop. In fact this flip-flop, introduces only a partial solution to the problem. The master/slave guarantees stability against oscillatory state changes and the dual mode anomalies, but does not prevent the 1’s and 0’s catching problem.

So a perfect solution will be to use devices which are edge-triggered or have a feature called data lock-out. These devices will allow the device to load the next state information into the flip-flop on an edge of the clock waveform and once this operation is complete, the effect of input changes are locked out until the next corresponding edge of the clock waveform arrives.

Conversion of one Type of FF to another type of FF:-

For converting one flip-flop to another type we require the understanding of the characteristic table and the excitation tables of each type of flip-flop.

Characteristic Table of Flip-Flops

Characteristic table of a flip-flop defines the logical property of the flip-flop and completely characterizes its operation. It has two columns one for input and another next state (Qn+1) column. Qn and Qn+1 illustrate the present and the next state. The table below shows the characteristic table of the SR, D, JK and T flip-flops.

Excitation Table of Flip-Flop

The excitation table is an important design aid, and the information plotted in this table is derived from the characteristic table. The excitation table helps in defining the inputs that will be responsible for that transition from present to next state.

To draw the excitation table, we assume that the present and the next state are known and then we determine the input combinations that will change the current state to the next state.

The excitation table of different flip-flops are given below:
Excitation table of SR Flip-Flop

The excitation table of a SR FF is given below. It is explained as follows.

Referring to the characteristic table of a SR FF, we see that to keep the FF in the same state we need to apply S=R=0, to set the FF we need apply S=1, R=0 and to reset it we need to apply S=0, R=1. Following this we get the following excitation table for the SR flip-flop.

Excitation Table for D Flip-flop:

Referring to the characteristic table of D-FF we can complete the excitation table for all the transitions from present state to the next state. That is to make the next state transition to ‘1’ we need to apply ‘1’ at D input, and to make the next state transition as ‘0’ we need to apply ‘0’ at D input. Excitation Table for D Flip-flop is given below:

Excitation table of JK flip Flop

Referring to the characteristic table we find that there are at least four different ways to change the state of the flip-flop.

Case1: If the current state Qt=0, and the next desired state is Qt+1=0. For this to happen we must apply either the input for no change J=K=0 or J=0, K=1 to reset the JK-FF. This means that the input J=0, K can be 0 or a 1 i.e. ‘x’.
Case 2: If the current state Qt=0, and the next desired state is Qt+1=1. For this to happen we must apply J=1, and K=0 or the toggle condition inputs J=1 and K=1. That is J must be 1, K can be 0 or 1.
Case 3: If the current state Qt=1, and the next desired state is Qt+1=0. For this to happen we must apply J=0 and K=1 or the toggle condition J=K=1..
Case 4: If the current state Qt=1, and the next desired state is also 1 i.e. Qt+1=1. For this to happen we must apply either the input for no change J=K=0 or condition for reset J=1, K=0. This means that we must apply K=0  and J can be 0 or a 1.
The excitation table of JK-FF is given below:

Excitation Table of T Flip-Flop

The characteristic table of the T flip-flop defines that Applying ‘0’ at T input will leave a T-FF in last state whereas applying a ‘1’ at T input will make the T-FF to toggle to next state. Using this characteristic we draw the excitation table of a T-FF as below:

Conversion from one type to another type of flip flop

At times it is required to convert one flip-flop into another type of flip-flop.  The block diagram for the conversion process is shown in figure:

Figure-1: Realization of one type of flip-flop from another flip-flop

Here we realize one type of flip-flop from another given flip-flop. The design procedure for such realization are:

1. Read the statement of flip-flop conversion carefully.
2. Write the characteristic equation for the desired flip-flop.
3. Write the excitation table of the given flip-flop, that fits for the present and next state.
4. Write the logic equation for the excitation table and simplify using K-Map.
5. Draw the logic circuit from the simplified equations.

Realize D flip-flop from the SR flip-flop

Step-1: The given SR FF has two inputs, but a D FF requires a single input that will be used.

Step-2: The truth table and the excitation table:

Input	transition present state to next		Inputs to be applied at SR as per Excitation table of Given (RS) Flip-flop
D	Qt	Qt+1	R	S
0	0	0	X	0
1	0	1	0	1
0	1	0	1	0
1	1	1	0	x

Step 3: Simplification of logic equations for R and S

Step 4: Draw the logic Diagram

The simplification of the Boolean equation for the excitation table variables are as obtained from the solution given above setp-3. The input D is connected to R input of the RS flip-flop through an inverter. The D input is directly connected to S input of the flip-flop.

Conversion of SR to JK Flip-flop

Step 1 Analysis: The desired JK flip-flop has two input, so the truth table will have four column i.e. J,K, Qn, and  Qn+1, The excitation table of the SR flip-flop will have two column. The entire table will have six columns.
Step 2: The truth table and the excitation table is shown below:

INPUTS		Present State	Next State	Inputs as per the Excitation table of SR FF
J	K	Qt	Qt+1	S	R
0	0	0	0	0	x
0	1	0	0	0	x
1	0	0	1	1	0
1	1	0	1	1	0
0	1	1	0	0	1
1	1	1	0	0	1
0	0	1	1	x	0
1	0	1	1	x	0

Step 3: the solution of the excitation table variables using the K-Map is shown below:

Step-4: Now after having obtained the equations for the  J and K input, we are in a position to draw the logic diagram of a SR to JK flip-flop.

Summary:

Latches and Flip-Flop are the sequential circuits. FF is a synchronous where latch operation is asynchronous. Latch an Flip-Flop are 1-bit memory element.

Flip-Flops switching timings are the set-up time, hold time and the propagation time.

Flip-Flop can be +ve edge, -ve edge or Level Triggered.

Characteristic table of a flip-flop defines the logical property of the flip-flop and completely characterizes its operation.

The excitation table is an important design aid, and the information plotted in this table is derived from the characteristic table. The excitation table helps in defining the inputs that will be responsible for that transition from present to next state.

Exercise

1. Differentiate between a Latch and a Flip-Flop.
2. Explain the operation of the SR, D, JK and T Flip-Flops with the help of the waveform
3. Write the characteristic table of D and JK Flip-Flop
4. Write the excitation table of SR and T Flip-Flop
5. Convert a D Flip-flop into a T Flip-Flop