History and Features of VHDL

The Requirement

The development of VHDL was initiated in 1981 by the United States Department of Defence to address the hardware life cycle crisis. The cost of re-procuring electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology.

Standardization

The standardization process for VHDL was unique in that the participation and feedback from industry was sought at an early stage. A baseline language (version 7.2) was published 2 years before the standard so that tool development could begin in earnest in advance of the standard. All rights to the language definition were given away by the DoD to the IEEE in order to encourage industry acceptance and investment.

ASIC Mandate

DoD Mil Std 454 mandates the supply of a comprehensive VHDL description with every ASIC delivered to the DoD. The best way to provide the required level of description is to use VHDL throughout the design process.

VHDL 1993

As an IEEE standard, VHDL must undergo a review process every 5 years (or sooner) to ensure its ongoing relevance to the industry. The first such revision was completed in September 1993, and this is still the most widely supported version of VHDL.

VHDL 2000 and VHDL 2002

One of the features that was introduced in VHDL-1993 was shared variables. Unfortunately, it wasn’t possible to use these in any meaningful way. A working group eventually resolved this by proposing the addition of protected types to VHDL. VHDL 2000 Edition is simply VHDL-1993 with protected types.

VHDL-2002 is a minor revision of VHDL 2000 Edition. There is one significant change, though: the rules on using buffer ports are relaxed, which makes these much more useful than hitherto.

VHPI

In 2007, an amendment to VHDL 2002 was created. This introduces the VHDL Procedural Interface (VHPI). The VHPI allows tools programmable access to a VHDL model before and during simulation. In other words, you can write programs in a language such as C that interact with a VHDL simulator.

VHDL 2008

The next revision of VHDL was released in January 2009, and is referred to as “VHDL-2008”. 

Features of VHDL

1. VHDL allows design entry in coded form, schematic and state diagram form.

2. Code in VHDL can be written in either lower case, upper case, i.e. it is a case insensitive language.

3. VHDL permits concurrent and sequential statements. All statements in the architecture are concurrent, but sequential statements are inside process, function and procedures.

4. VHDL is an event driven language, whenever an event occur on a signal all statements that have a reference to that signal will be affected and thus executed.

5. VHDL is a platform independent language, and portable that is, it allows different vendors to use the same design description

6. It supports both synchronous and asynchronous timing models.

7. It supports both predefined and user defined data types.

8. It is strongly typed language, i.e. one in which each type of data is predefined as part of the programming language and all constants or variables defined for a given code must be described with one of the data types.

9. It allows design verification at three levels i.e. compilation and simulation, synthesis and post synthesis level.

10. A digital system can be modelled using concurrent (data flow), behavioural (sequential) and structural modelling styles.

11. The use of packages, user defined libraries, functions and procedures allows code reusability.

12. It includes a number of CAD tools such as tools for design entry, simulation and synthesis tools.

13. Test bench can be written in the same language. This permits assigning all possible test cases for the design for the purpose of simulation thus automating the test.

Modelling of Digital System

Introduction to Hardware description languages

A hardware circuit under synthesis is considered to be an entity. An entity ( digital circuit) is modeled in VHDL using an entity declaration and the one or more or mix architecture. The relationship among these is shown in figure 2.1.

Figure 2.1: A VHDL Module

An entity uses primary and the secondary constructs.  The primary constructs are package, configuration and entity declaration. Secondary constructs comprise architecture and the package body. These constructs are explained below:

Design Entity: represents VHDL model’s basic element. It could represent a whole system, a PCB (Printed Circuit Board), an IC or a gate). An entity (hardware system) is modeled using the entity declaration and at least one architecture body.

Whereas an entity describe the hardware from external point of view (number of input and outputs), architecture describes the internal view of the hardware i.e how it behaves i.e. as a set of interconnected components or a set of statements (concurrent or sequential). An entity-A when used inside another entity-B becomes as a component of entity-B, so a component is also an entity depending on the level of abstraction used.

The digital system can be represented in different forms such as a behavioral model or a structural model. Most commonly known as levels of abstraction, these levels help the designer to develop complex systems efficiently.

Structural Architecture: Architecture may be described as structure of the design in terms of its sub-components and their interconnections. Structural level describes the systems as gates or component block interconnected to perform the desired operations. Structural level is primarily the graphical representation of the digital system and so it is closer to the actual physical representation of the system.

Behavioral Model: Behavioral level describes the system the way it behaves instead of a lower abstraction of its connections. Behavioral model describes the relationship between the input and output signals. The description can be a Register Transfer Level (RTL) or Algorithmic (set of instruction) or simple Boolean equations.

Dataflow Architecture/ Register Transfer Level: This is mostly used for design of combinational logics. This type of architecture contains only the concurrent statements which execute when the data become available on their inputs. Whenever an input is available, all instructions using that input execute irrespective of the order or place of the instruction inside that architecture.

Algorithmic Level/ Sequential: Algorithmic level is mostly used for design of sequential logics. In this type of architecture, the functional and possibly timing characteristic is described using VHDL concurrent statements and processes. The process itself is the concurrent statement but all the statements within a process are sequential and execute in sequential order until it gets suspended by a wait statement.

 Packages: are a collection of common declaration, constants, and/or subprograms to entities and architectures.

Generics: provide a method for communicating information to architecture from the external environment. They are passed through the entity construct.

Ports: Ports provide the mechanism for a device to communicate with its environment. A port declaration defines the names, types directions and possible default values for the signals in a component’s interface.

Configuration:
Configuration is used configure an entity. That is it binds one of the many architecture to an entity. Configuration may also specify binding of component(s) of a selected architecture to an entity. The figure below shows the use of configuration:

Here, in figure (A) architecture-3 is bound with Entity-1 and in figure(B) architecture-1 is bound to Entity-2, Also the component X of architecture-3 of figure (A) is configured to be bound to entity-2 and component Y of architecture-1 in figure (B) is configured to be bound to Entity-3. Thus, the configuration is used for binding or architectures and components to an entity. Configuration of architecture and component with an entity is shown by bold arrow.

Questions

• What is the purpose of the hardware description language (HDL)?

• Write the history of the VHDL

• Write the features of VHDL

• How is an entity modelled in VHDL?