Structure of VHDL Code


Structure of VHDL Code

A general structure of the VHDL code is shown in figure

Figure 3.1: General Struture of VHDL Code

Structure of VHDL program

–Library clause is used to declares the name as a pre-defined/or user-defined library.

LIBRARY<library_Name>; — Library IEEE will be used almost in every code

— we need to import one or more packages from different libraries as given below

USE<library_name>.<package_name>.ALL; –this is the format for importing packages

USEIEEE.STD_LOGIC_1164.ALL; — this package is required for bit, std_logic,

–& std_logic_vector declarations and some related operations

— arithmetic functions with Signed or Unsigned values


— then we declare the entity


–the entity can have generic for constant declaration and input output port declaration

GENERIC( generic_name : generic_type : generic_value);



<signal_name> : mode <type>;

<signal_name> : mode <type> := default_value;

<signal_name> : INOUT<type>;

<signal_name> : OUT<type> := <default_value>



— Next we write the architecture for the entity

ARCHITECTURE<architecture_name>OF <Entity_name>IS

— declaration of optional signals, constants etc;


–here come the statement that describe the behaviour of the design

–commonly used statements are:

–Optional Concurrent signal Assignment

–Optional Process Statement

–Optional Conditional Signal assignment statement

–optional Generate statement

end [Architecture_name];

Description of the VHDL code

Entity Declaration: having all the input output declarations, second the architecture describing the functionality of the entity in response to the inputs. The general syntax of the entity declaration is:

Entity entity-name

Generic (constant constant_name: constant_type := value);


–port declarations


end entity <entity-name>

Naming Rules

The value entity_name can be any name that you pick provided it meets certain constraints. These rules or constrains are:

  • Begin with a letter.
  • Consist of letters, numbers, or the underscore character.
  • Can not end with an underscore.
  • Cannot have two consecutive underscores.
  • Are case insensitive (ie. MY_ENTITY = my_entity=My_Entity )
  • Cannot be a reserved word.


Architecture assigned to an entity describes internal relationship between input and output ports of the entity. The architecture consists of two parts:

An optional declaration part : All declarations are made between the architecture and begin, and may contain declarations of types, signals, constants, subprograms (functions and procedures), components, and groups. An example of declarations inside architecture is given below:

architecture architecture_name of entity_name is

variable x: std_logic;

signal clock: std_logic;

constant xyz: bit:=1;

Type myInt is range 0 to 1024;

Type hex_digit is (‘0’,’1’,’2’,’3’,’4’,’5’,’6’,’7’,’8’,’9’,’A,’B’,’C’,’D’,’E’,’F’);

Type four_value is (‘0’,’1’,’Z’,’U’);

— We can then use the above type as

Variable X : myInt;

Variable digit : hex_digit:=’A’;

Signal Y : four_value;


Architecture Body: The architecture body of an entity contains a list of statements which define the relationship between different inputs and outputs. The different types of statements inside the architecture body between the begin and end can be of following types:

concurrent signal assignment;

process statement;

component instantiation;

concurrent procedure call;

generate statement;

concurrent assertion statement;

block statement;

Given below is a sample code for an AND gate

entity AND_gate is

port ( A, B : in std_logic;

Y : out std_logic );

End AND_gate;

Architecture behave of AND_gate is


Y <= A and B;

end [ architecture ] [ architecture_name ];

Architecture body can be written in the following different styles

  • Concurrent or Dataflow Modelling
  • Behavioral (functional)
  • Structural Modelling
  • or mixed Style Modelling


Which of the following entity name are correct

1. EC262 2. Slippery_fish 3. Project_25

4. Big_chickens 5. 2bae_surprise_quiz 6. _bae_surprise_quiz

7. bae_surprise_quiz_8. bae__surprise_quiz 9. disconnect

  • Describe various basic terminologies used in VHDL (Entity, Architecture, Configuration, Package, Driver, Bus, Attribute, Generic, Process)

  • Write the structure of the VHDL program

  • Describe the entity declaration syntax and explain each part. ( Library Declaration, PORT(direction and a type), Signal), Architecture)

  • Difference between std_logic and std_ulogic

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