Interrupts in 8051

What is an Interrupt: It is a requesting mechanism for the peripherals to make the microcontroller interrupt the currently executing program and run the program to service the request. The program that is run upon the interrupt is called an ISR (interrupt service routine)

Types of Interrupts in 8051

There are five different sources of interrupts

A real life example – Before going to sleep, you set the timer. Then forget what the timer does, and go for sleep. When the timer finishes the counting, it alarms and interrupts you from sleep. You then wake and starts doing your routine.

sources of interrupt in 8051 are:

1. Timer-0: Timer-0 interrupts
2. Timer-1: Timer-1 interrupts
3. Serial Rx/Tx
4. INT0
5. INT1

All interrupts in 8051 are vectored interrupts

Interrupt type	Flag	Vector Address
External INT0	IE0	0003h
Timer-0	TF0	000Bh
External INT-1	IE1	0013h
Timer-1	TF1	001Bh
Serial Interrupt	RI/TI	0023h

** By default, when you restart your system (8051 based), IP point to address 0000 in the program memory. The memory map can be seen in following figure.

IE  – interrupt Enable register (SFR)

interrupt Enable register (SFR)
D7	D6	D5	D4	D3	D2	D1	D0
EA			ES	ET1	EX1	ET0	EX0
Enable All Interrupts	X	X	Serial Interrupt Enable	Timer-1 Interrupt Enable	External EX-1 Interrupt Enable	Timer-0 Interrupt Enable	External EX-0 Interrupt Enable
1-Enable 0-Disable	x	x	1-Enable 0-Disable	1-Enable 0-Disable	1-Enable 0-Disable	1-Enable 0-Disable	1-Enable 0-Disable

 

If the interrupt are to be allowed, EA bit of the IS register must first be set to ‘1’. This is global enable of the registers. Setting bit-7 of the ISE register enables all the interrupts that have been selected by setting other bits of the IE register.

Interrupt Priority:

After execution of every instruction, 8051 evaluates whether an interrupt should occur. The following interrupt sequence or condition is checked by the hardware:

• External Interrupt-0
• Timer-0 interrupt
• External Interrupt-1
• Timer-1 interrupt
• Serial interrupt

There are two levels of the priority in 8051; these are high and low level priority. The priority level can be set to high or low in the interrupt priority SFR.

If two interrupt of same priority occur, then the priory is decided by the interrupt sequence by the hardware. While a high level and low level interrupt occur at the same time, the interrupt having high priority will be executed. If two high level interrupts occur ate the same time the priority among these will be decided by the hardware interrupt sequence. The format of the interrupt Priority SFR (IP) is shown below:

interrupt Priority SFR
Bits	D7	D6	D5	D4	D3	D2	D1	D0
Bit Address	–	–	–	BC	BB	BA	B9	B8
Bit Name	EA	x	X	PS	PT1	PX1	PT0	PX0
Description	Global Interrupt Enable	Don’t care		Serial interrupt priority	timer-0 interrupt priority	Ext-0 interrupt priority	timer-0 interrupt priority	Ext-0 interrupt priority