Loop statements are a catagory of control structures that allow you to specify repeating sequences of behavior in a circuit. The statement are used for iterating a well-defined task. In each iteration it then increaments or decrement some local identifier for use inside the LOOP statement. VHDL has following types of iterative statements

i. FOR statement

ii. WHILE statement

iii. and infinite loops

Syntax for the iteration statements:

i. FOR statement

[label :] FOR index in <range> LOOP

Statement(s);

End LOOP;

Example-1: Synthesize a 4-bit Incrementer in sequential modelling in VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity incrementer is

generic(N: integer:=6);

port (

a : in STD_LOGIC_VECTOR (N downto 0);

b : out STD_LOGIC_VECTOR (N downto 0)

);

end incrementer;

architecture Behavioral of incrementer is

begin

process(a)

variable x: std_logic_vector(N downto 0);

begin

b(0) <= NOT a(0);

x(0) := a(0);

for I in 1 to N LOOP

x(i) := a(i) and x(i-1);

b(i) <= a(i) xor x(i-1);

end loop;

end process;

end Behavioral;

example-2: The following VHDL code synthesizes a 8-bit parity generator

library ieee;

use ieee.std_logic_1164.all;

entity parity10 is

port(

D: in std_logic_vector(0 to 9);

ODD: out std_logic

);

constant WIDTH: integer := 10;

end parity10;

architecture behavior of parity10 is

begin

process(D)

variable otmp: Boolean;

begin

otmp := false;

for i in 0 to D’length – 1 loop

if D(i) = ‘1’ then

otmp := not otmp;

end if;

end loop;

if otmp then

ODD <= ‘1’;

else

ODD <= ‘0’;

end if;

end process;

end behavior;

In this example the length of the vector is determined by “D’length” and used for the index variable.

WHILE LOOP

While loop is the second type of iteration scheme. In this scheme the loop condition is written as an expression after the while keyword.

Syntax :

{LABEL : ] WHILE (expression) LOOP

Statement(s);

END LOOP;

Example-1:

The example below illustrates the use of the while loop:

architecture Behavioral of incrementer is

begin

process(a)

variable x: std_logic_vector(N downto 0);

begin

b(0) <= NOT a(0);

x(0) := a(0);

while (I < N ) LOOP

x(i) := a(i) and x(i-1);

b(i) <= a(i) xor x(i-1);

end loop;

end process;

end Behavioral;

EXIT

The exit statement is used to finish or exit the execution of an enclosing loop statement. If the exit statement includes a condition, then the exit from the loop is conditional.

The exit statement is of the following type:

• • exit;
  • exit loop_label;
  • exit loop_label when condition;

Example 1

Loop_1:  for count  in 1 to 10 loop
exit Loop_1 when reset = ‘1’; — conditional exit

A (count) := ‘0’;

           end loop Loop_1;

B <= A after 10 ns;

 At the beginning of each iteration of the LOOP_1 loop, the reset =’1′ condition is checked. If the condition is FALSE, then the rest of the loop is executed. Otherwise, the control is passed to the next statement after the loop i.e B<= A after 10 ns.

Example 2

Loop_X: loop
a_v := 0;
Loop_Y:    loop
Exit_1:       exit Loop_X when condition_1;
Output_1(a_v) := Input_1(a_v);
a_v := a_v + 1;
Exit_2:       exit when condition_2;
    end loop Loop_Y;
Assign_Y: B(i) <= Output_1(i) after 10 ns;
Exit_3:    exit Loop_X when condition_3;
end loop Loop_X;
Assign_X: A <=B after 10 ns;

There are two nested loops in the above example.

When the condition_1 is TRUE, the Exit_1 statement will be executed. This will cause termination of the Loop_X loop and moving the execution to Assign_X. Next, the Loop_X will be terminated because its label is explicitly listed in the exit statement.

If condition_1 is FALSE then the two assignments below it are performed and condition_2 is checked. If it is TRUE, then the Loop_Y is exited. Since there is no loop label within the exit statement, therefore it relates to the innermost loop. As a result, the next statement to be executed will be Assign_Y.

Finally, when the condition_3 is TRUE the Loop_X is terminated. The Exit_3 loop label could be skipped because this statement is within the boundaries of the exit Loop_X loop.

NEXT Statement

Next statement is used to iterate back to the top of the LOOP statement, when a condition specified after the next statement become true, the statements that follow the NEXT statements are skipped and the control passed for the next iteration.

The next statement is of the following types:

• next;
• next loop_label;
• next loop_label when condition

examples-1:

Loop_Z:  for count_value in 1 to 8 loop
Assign_1:  A(count_value) := ‘0’;
           next when condition_1;
Assign_2:  A(count_value + 8) := ‘0’;
         end loop Loop_Z;

If the condition_1 in the iteration count_value is TRUE, then the next statement will be executed. The next statement to be executed will be Assign_1 in the iteration count_value+1. Otherwise, the sequence of operations is as specified, i.e. Assign_2 is executed.

Example 2

Loop_X: for count_value in 1 to 8 loop
Assign_1: A(count_value) := ‘0’;
k := 0;
Loop_Y:    loop
Assign_2: B(k) := ‘0’;
              next Loop_X when condition_1;
Assign_3: B(k + 8) := ‘0’;
k := k + 1;
           end loop Loop_Y;
        end loop Loop_X;

If condition_1 is TRUE, then the next statement is executed and the control goes to the assignment statement labeled Assign_1 in the next iteration of Loop_X. If not, then the iteration is continued with Assign_3, causing incrementing k.

Self Practice

• Explain LOOP statements in VHDL. (a) LOOP, (b) While (c) without any iteration scheme(also Arrays)
• Write short note on attribute and its usage with example.
• Describe Exit statement.
• What is the purpose of Next statement explain with example