Synthesis of Decoders in VHDL

Decoder Design using VHDL

Objective:

  1. To learn how to write VHDL code
  2. To Learn how to do functional simulation
  3. To do study of the synthesis done by VHDL and the theoretical desin obtained using algebraic solution.

Requirement:

A computer system installed with XILINX VHDL Theory:

Theory:

A decoder generally decodes a binary value into a non-binary one by setting exactly one of its ‘ n’outputs to logic “1”.

If a binary decoder receives n inputs (usually grouped as a single binary or Boolean number) it activates one and only one of its 2n outputs based on that input with all other outputs deactivated.

Figure: Decoder Symbols

 

The truth table of a 2×4 decoder is shown below:

 

S1 S0 O0 O1 O2 O3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

 

As seen in the truth table only one of the output line is active depending on the input line combination. The logic equations for a decoder can be written as:

 

O0 : S1’S0 -> ‘1’ when S1=0 and S0=0
O1 : S1’S0 -> ‘1’ when S1=0 and S0=1
O2 `: S1S0 -> ‘1’ when S1=1 and S0=0
O3 : S1S0 -> ‘1’ when S1=1 and S0=1

 

Now using the above expressions we can write the VHDL code for any size of decode. Here we implement a 1: 2 decoder with and without enable input. Then use these as building block for constructing larger size deciders.

Synthesis

Dataflow Modeling Decoder without Enable

1 Decoder without enable

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity decod is

Port (

sel : in STD_LOGIC;

o1 : out STD_LOGIC;

o2 : out STD_LOGIC);

end decod;

architecture Behavioral of decod is

begin

— note how two ways of concurrent statements are written

–O2 with when statement

–O1 is written using select statement

O2 <= ‘1’ when sel =’1′ else ‘0 when sel=’0’;

with sel select

O1 <= ‘1’ when ‘0’,

‘0’ when ‘1’

‘Z’ when others

end Behavioral;

 

Dataflow Modeling Decoder with Enable

2 Decoder with enable input

Figure: Decoder with enable

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity decoder_with_enable is

Port (

sel : in STD_LOGIC;

en : in STD_LOGIC;

o1 : out STD_LOGIC;

o2 : out STD_LOGIC

);

end decoder_with_enable;

architecture Behavioral of decoder_with_enable is

begin

o1 <= ‘1’ when sel=’0′ and en=’1′ else ‘0’;

o2 <= ‘1’ when sel=’1′ and en=’1′ else ‘0’;

end Behavioral;

structural Modeling

2:4 Decoder using 1:2 Decoder in structure modelling

Figure: Structural Syle Decode

 

VHDL Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity decoder2to4_structure is

Port (

I : in STD_LOGIC_VECTOR (1 downto 0);

o : out STD_LOGIC_VECTOR (3 downto 0));

end decoder2to4_structure;

architecture Behavioral of decoder2to4_structure is

signal w1, w2: std_logic;

begin

x1: entity work.decod PORT MAP (

sel=>i(1), o1=> w1,o2=> w2

);

x2: entity work.decoder_with_enable PORT MAP (

sel=>i(0), en=> w1, o1=> o(0), o2=> o(1)

);

x3: entity work.decoder_with_enable PORT MAP (

sel=>i(0), en=> w2,o1=> o(2), o2 => o(3)

);

end Behavioral;

 

RTL View:

 

The snapshot shows the top level design of 1 2:4 decoder wit I(1:0) being the inputs and o(3:0) being the outputs.

Figure: RTL View of a decoder synthesized using Structural Style

Simulation

Figure: Simulation

Updated: August 11, 2019 — 3:08 pm

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