Sequential style of modeling is also called the behavioral style. This style of coding make use of the process statement(s). Once an entity is declared, the a process is defined inside the architecture. Sequential code inside the process allows statements like IF, CASE, LOOP and WAIT and the desired operators inside the code.The general structure of a behavioural style modelling in VHDL is given below: LIBRARY <library_name>; USE library_name.<package_name>.all; ENTITY <entity_name> IS PORT( Signal_name(s) : mode type ; Signal_name : mode type ); END [ENTITY] [entity_name] ; ARCHITECTURE behavioural OF<entity_name> IS --declaration of signal, constant, type; BEGIN --concurrent statement --[process_label :] PROCESS [(sensitivity list)] --variable, constant declarations; BEGIN Sequential_statement(s); End PROCESS[process_label ]; END [Architecture] [behavioural]; As seen in the above prototype VHDL code, a sequantial code need a process statement. To make the code  sequential,te statements have to be