ASSERT Statement in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 14, 20210 ASSERT Statement ASSERT statement is used to display message of some types that may be generated by the system when a certain condition such as a fault occur in the system. Thus, it serves as an exeption handling instruction within a program and is most often used for test purposes. Assertion can be used to terminate the execution of a simulation upon a pre-defined fault class. For this a condition is defined, which should be fulfilled in normal operation mode. If this is not the case a fault message may be generated. Syntax of ASSERT statement is: assertion statement ::= [ label : ] assertion ; assertion ::= ASSERT condition [ REPORT expression ] [ SEVERITY expression ]; User defined text messages are