Lecture-3 Structure of VHDL Code A general structure of the VHDL code is shown in figure Structure of VHDL program --Library clause is used to declares the name as a pre-defined/or user-defined library. LIBRARY<library_Name>; -- Library IEEE will be used almost in every code -- we need to import one or more packages from different libraries as given below USE<library_name>.<package_name>.ALL; --this is the format for importing packages USEIEEE.STD_LOGIC_1164.ALL; -- this package is required for bit, std_logic, --& std_logic_vector declarations and some related operations -- arithmetic functions with Signed or Unsigned values USEIEEE.NUMERIC_STD.ALL; -- then we declare the entity ENTITY<entity_name>IS --the entity can have generic for constant declaration and input output port declaration GENERIC( generic_name : generic_type : generic_value); PORT ( <signal_name> : mode <type>; <signal_name> : mode <type> := default_value; <signal_name> : INOUT<type>; <signal_name>