Operator Overloading in VHDL Digital Design using VHDL by Ravinder Nath Rajotiya - May 13, 2021May 13, 20210 At times, the coder need to use the same operator for processing objects of different type. For example, VHDL has a predefined operator '+' to add two integers, what is we add two characters, add two real values, add two strings, add two vectors and so on. VHDL and any other language do not have seperate operator for those purpose and thus would demand for a separate operator. As the number of operators increase it’ll be hard to remember them. Definition Overloading allows the coder to write separate subprograms for the same object (operator) to perform on values of different types. An operator is overloaded by defining a functionality other than its pre-defined meaning. This is done by defining a function and the