VHDL Modeling Styles Concurrent or Dataflow Modelling: The Dataflow description is built with concurrent signal assignment statements. Each of the statements can be activated when any of its input signals changes its value. This is shown with the help of a 2-to-4 decoder. The output of the decoder is used to illuminate one of the four LEDs. The entity is given in the following code in VHDL Entity Decoder_bcd is Port ( A, B : in std_logic; O : out std_logic_vector( 3 downto 0) ); End entity Decoder_bcd; architecture Dataflow of Decoder_bcd is begin O(3) <= A and B; O(2) <= A and (not B); O(1) <= (not A) and B; O(0) <= (not A) and (not B); end Dataflow; All the four statements here are executed concurrently and each of them is activated individually when any of its input signals changes its value. 2. Behaviour (Functional) Model: The architecture body describes